LSIS XBC-DR14E - Page 41

T
he following table shows the general specifications of the XGB compact type CPU
(XBC-Dx20/30/40/60SU).
Items
Specifications (“SU” type)
Remark
XBC-DR20SU
XBC-DR30SU
XBC-DR40SU
XBC-DR60SU
XBC-DN20SU
XBC-DN30SU
XBC-DN40SU
XBC-DN60SU
XBC-DP20SU
XBC-DP30SU
XBC-DP40SU
XBC-DP60SU
Program control method Reiterative operation, fixed cycle operation, constant scan
-
I/O control method
Scan synchronous batch processing method (Refresh method),
Directed by program instruction
Program language Ladder Diagram, Instruction List
Number of
instructions
Basic 28
Application 687
Processing speed
(Basic instruction)
94 ns/Step
Program capacity 15 k steps
Max. I/O points
244 point
(Main + Expansion
7 stages)
254 point
(Main
+ Expansion
7 stages)
264 point
(Main
+ Expansion
7 stages)
284 point
(Main
+ Expansion
7 stages)
Data area
P P0000 ~ P1023F (16,384 point)
M M0000 ~ M1023F (16,384 point)
K K0000 ~ K4095F (65,536 point)
L L0000 ~ L2047F (32,768 point)
F F0000 ~ F1023F (16,384 point)
T
100ms, 10ms, 1ms : T0000 ~ T1023 (1,024 point)
(Adjustable by parameter setting)
C C0000 ~ C1023 (1,024)
S S00.00 ~ S127.99
D D0000 ~ D10239 (10,240 word)
Word
U U00.00 ~ U0A.31 (Analog data refresh area: 352 word)
Z Z000~Z127 (128 Word)
R R0000~R10239 (10,240 word)
Total program 128
-
Initial task 1
Cyclic task Max. 8
I/O task Max. 8
Internal device task Max. 8
Operation mode RUN, STOP, DEBUG
Self-diagnosis function Detects errors of scan time, memory, I/O
Program port RS-232C 1 channel, USB 1 channel
Back-up method Latch area setting in basic parameter
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