Programming Overview
UG0451 User Guide Revision 7.0 8
For board level design, it is important to know the state of these interfaces during reset. The following
table summarizes the state of these interfaces during different reset.
2.2 Programming Bitstream Generation
The Libero SoC software is used to generate the programming bitstream formats required to support the
different programming modes. Table 5, page 10 shows the different bitstream file types and sizes for
SmartFusion2 and IGLOO2 devices.
Programming is integrated into the Libero SoC software design flow. With the enhanced Libero SoC
design flow, you can program the device directly, without launching the programming software tool
(FlashPro) separately. When the design is ready for production, the programming bitstream can be
exported using the Libero SoC software.
Note: FlashPro cannot be invoked from within the Libero SoC software for SmartFusion2 and IGLOO2 devices.
The programming bitstream contains the following components, which can be selected during bitstream
generation:
• Images of FPGA fabric only
• Full or partial image of eNVM only
• Custom Security
Custom security can be implemented in the bitstream from Configure Security under Program and Debug
Design Options menu of the Design flow in the Libero SoC software.
When the bitstream is exported the digest of the selected components is printed in the Libero log window
and saved in a file under the export folder. This digest can be used to verify whether intended bitstream
was used during programming or not. For more information, see the "Digest-Based Verification Method"
section of the SmartFusion2 and IGLOO2 FPGA Security Best Practices User Guide.
The following figure shows the Libero SoC programming bitstream generation flow. There are two
programming options:
• Option 1: The programming bitstream file is generated by clicking Generate Programming Data.
SmartFusion2 and IGLOO2 devices can be programmed from within the tool, provided the target
board is connected with the FlashPro4/FlashPro5 programmer. Option 1 is used for JTAG
programming mode.
• Option 2: After implementation of the design, the appropriate programming bitstream can be
exported and later used in any of the supported programming modes.
Table 4 • State of Programming Interface During Reset
Programming
Interface
During Power on
Reset
During
DEVRST_N
1
1. DEVRST_N is an asynchronous reset pin and must be asserted only when the device is unresponsive because of some
unforeseen circumstances.Do not assert the DEVRST_N pin during programming operation, which might cause severe
consequences including corrupting the device configuration.
During System Control
Reset During MSS Reset
JTAG port JTAG I/Os are
enabled
JTAG I/Os are
enabled
JTAG I/Os enabled, but not
functional as JTAG operation
within the system controller
relies on TRSTB being
negated but held asserted for
system controller’s suspend
mode
Unaffected
System control SPI port
(SC_SPI)
Disabled (floating,
no pull ups)
Disabled
(floating, no
pull ups)
Active but not functional Unaffected
MSS/HPMS SPI_0 port Disabled (floating,
no pull ups)
Disabled
(floating, no
pull ups)
Depends on user
configuration
Depends on user
configuration
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