SPI Slave Programming
UG0451 User Guide Revision 7.0 19
4 SPI Slave Programming
In the SPI slave programming mode, an external SPI master programs the SmartFusion2 or IGLOO2
devices. The SPI master can be an external microprocessor or a programmer such as FlashPro5. The
SPI master interfaces with the system controller through a dedicated SC_SPI port, which is in SPI slave
mode by default. The system controller operates in a fixed SPI mode, 3 (SPO/CPOL= SPH/CPHA =1).
For specific device or package support of the SC_SPI port, see Tab le 3, page 7. Microsemi DirectC-SPI
programming must be used with an external microprocessor that acts as a master to program the
SmartFusion2 or IGLOO2 devices in the SPI-Slave mode. For more information, see the SPI-DirectC
Solution User Guide.
4.1 Programming Interface Overview
The system controller’s dedicated SC_SPI port is located in different bank numbers based on the die or
package. See the pin tables of the respective devices for the bank numbers. These ports are part of
MSIOs. The bank must be powered up before programming in SPI mode. The following table provides
description of the dedicated SC_SPI pins.
4.1.1 Design Implementation
The following figure shows the recommended board configuration for SPI slave programming using an
external microprocessor. The command protocol used on the SPI Slave programming is similar to the
JTAG command protocol. The target board must provide power to the VPP, VPPNVM, VDD, and VDDIOx
(where x = SC_SPI bank number) pins.
For the recommended voltage ranges and pin locations, see the SmartFusion2 and IGLOO2 Datasheet
and the corresponding package pin assignment table.
You do not need to reset the FPGA after programming; the DirectC algorithm resets it after the
programming is completed. For information about the I/O states during SPI slave programming, see
State of SmartFusion2 and IGLOO2 Components During Programming, page 42.
Note: During JTAG or SPI-Slave programming, do not run any of the AES/DRBG/ECC Point Multiplication
system services when System controller is processing the initial component of the bitstream (BITS). The
system service may corrupt the bitstream information if the user design requests AES/DRBG/ECC Point
Multiplication system services. This issue does not exist in Auto-update, IAP or Programming recovery. If
these security system services must be run during programming, you must generate a STAPL/DAT file
using Libero 11.8 SP3 or contact soc_tech@microsemi.com to use older Libero versions.
Table 7 • Dedicated SC_SPI Pins
1
1. If unused, these pins must be left floating. These pins have internal pull up
activated after the device is powered up.
Name Polarity Direction Descriptions
SC_SPI_SS Low In SPI slave select
SC_SPI_SDO High Out SPI data output
SC_SPI_SDI High In SPI data input
SC_SPI_CLK High In SPI clock
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