Microsemi IGLOO2 - State of SmartFusion2 and IGLOO2 Components During Programming

State of SmartFusion2 and IGLOO2 Components During Programming
UG0451 User Guide Revision 7.0 42
11 State of SmartFusion2 and IGLOO2
Components During Programming
The following table lists the state of each ASIC block and I/O during the programming modes described
in this user guide. You can configure the I/O state during JTAG programing in Libero SoC, see Figure 22,
page 44. For more information, see the Libero SoC User Guide.
Note: I/O state of a blank device is tristated with weak pull up. During reset, the I/Os are floating even if pull up
is enabled or I/O has a default pull up. However, for the SC_SPI and JTAG pins, the pull up is active
during reset because they are hardwired.
Table 26 • ASIC Block and I/O State During Programming
Component
Programming Method
JTAG/SPI Slave IAP/MSS ISP Auto Programming
Cortex-M3
processor
Held in reset Operational, running user
firmware
Held in reset
MSS/HPMS
(without Cortex-
M3)
Active during programming to
allow programming access to
eNVM.
Active Active during programming to
allow programming access to
eNVM.
MDDR
controller
DDR I/O calibration block held
in reset.
DDR I/O calibration block held in
reset.
DDR I/O calibration block held
in reset.
Shared I/O
(fabric/MSS/HP
MS) except
SPI_0
I/Os are tristated by default
during JTAG programming, but
can be configured to user-
selectable states in Libero SoC
(see Figure 22, page 44).
During SPI slave programming
of a blank device, I/Os are
tristated with weak pull up. If the
device is already programmed,
then the I/O state will be
according to the user-
configured F*F state.
The device has been
programmed already once,
therefore, I/O state will be
according to the user-configured
F*F state.
Tristated with weak pull up.