Microsemi IGLOO2 - Page 48

State of SmartFusion2 and IGLOO2 Components During Programming
UG0451 User Guide Revision 7.0 43
SPI_0 Same as above Same as above for MSS ISP.
For IAP, slave select pins (SS4,
SS5, SS6, and SS7) of the SPI_0
port will drive high (except 005
and 010 devices). The I/O level
and drive strength are based on
the previous settings
programmed into the device. All
other SPI_0 I/O will be tristated
with weak pull up.
Slave select pins (SS4, SS5,
SS6, and SS7) of SPI_0 the
port will drive high (except 005
and 010 devices). The I/O level
will be the same as bank
voltage used for SPI_0 bank
and the drive strength will be
maximum for this I/O level. For
example, if the SPI_0 bank was
powered by 1.8 V, then the
drive strength will be the
maximum value allowed for 1.8
V LVCMOS I/O. For the
maximum drive strength
allowed for LVCMOS 1.8 V
transmitter, see the
SmartFusion2 and IGLOO2
Datasheet. All other SPI_0 I/O
will be tristated with weak pull
up.
Shared I/O
(Fabric/MDDR)
Tristated
1
Tristated
1
Tristated with weak pull up
Shared I/O
(fabric/FDDR)
Tristated
1
Tristated
1
Tristated with weak pull up
Dedicated fabric
I/O
Tristated
1
Tristated
1
Tristated with weak pull up
SERDES I/O Unaffected by programming Unaffected by programming Unaffected by programming
FDDR block Fabric interfaces to this block
are gated off. So no
transactions can occur at
configuring APB, AHB/AXI
interfaces to the fabric.
Fabric interfaces to this block are
gated off. So no transactions can
occur at configuring APB,
AHB/AXI interfaces to the fabric.
Fabric interfaces to this block
are gated off. So no
transactions can occur at
configuring APB, AHB/AXI
interfaces to the fabric.
SERDESIF
block
Fabric interfaces to this block
are gated off. So no
transactions can occur at
configuring APB, AHB/AXI
interfaces to the fabric.
Fabric interfaces to this block are
gated off. So no transactions can
occur at configuring APB,
AHB/AXI interfaces to the fabric.
Fabric interfaces to this block
are gated off. So no
transactions can occur at
configuring APB, AHB/AXI
interfaces to the fabric.
1. I/O state during JTAG programming can be configured differently, see Figure 22, page 44. I/0 states during SPI slave
programming, MSS ISP, and IAP follow user-configured F*F state (see Use of Flash Freeze Mechanism in Device Programming,
page 45).
Table 26 • ASIC Block and I/O State During Programming (continued)
Component
Programming Method
JTAG/SPI Slave IAP/MSS ISP Auto Programming