JTAG Programming
UG0451 User Guide Revision 7.0 13
3JTAG Programming
SmartFusion2 and IGLOO2 devices support programming using a dedicated JTAG port. The system
controller implements the functionality of a JTAG slave and complies to IEEE 1532 and IEEE 1149.1
standards. The JTAG port communicates with the system controller using:
• A command register that sends the JTAG instruction to be executed.
• A 128-bit data buffer that transfers any associated data.
To start programming using JTAG, the device must not be in Flash*Freeze (F*F) mode. When a device is
not in a programmed state, all user I/O pins are disabled, that is, tristated. This is achieved by keeping
the global IO_EN signal internal signal deactivated, which disables the input buffers. I/O states during
JTAG programming can be configured in Libero SoC. For more information, see State of SmartFusion2
and IGLOO2 Components During Programming, page 42.
3.1 Programming Interface Overview
SmartFusion2 and IGLOO2 devices can be programmed through the dedicated JTAG interface. An
external programmer (such as FlashPro4/5) or a microprocessor is used to program the device. The
devices can be programmed in both single and chain modes. SmartFusion2 and IGLOO2 devices have
JTAG pins in a dedicated bank. The location of the bank varies depending on the package. For more
information about the bank and its location, see SmartFusion2 Pin Descriptions.
JTAG signals can be operated at 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V. Therefore, the JTAG bank voltage
can be set to any of these voltages. The logic level of the JTAG signals depends on the JTAG bank
voltage. The following table lists the JTAG pin names, descriptions, and their termination details.
Note: If the JTAG programming mode is not used, JTAG pins must be terminated.
Table 6 • JTAG Pin Names and Description
Name Direction
Weak
Pull Up Termination Description
JTAGSEL Input Yes Terminate with
1 K pull up to
JTAG power
supply
JTAG controller selection.
If JTAGSEL is pulled high, an external TAP controller
connects the JTAG interface to the system controller TAP.
This is the recommended setup for programming and
microcontroller debug through SoftConsole.
Tie to GND
through 1 K
If JTAGSEL is pulled low, an external TAP controller
connects to either the Cortex-M3 JTAG TAP (if debug is
enabled) or an auxiliary TAP (if debug is disabled).
This is the recommended setup for microcontroller
debugging using tools such as IAR or KEIL (SmartFusion2
only). For IGLOO2 based designs, this signal must be held
high through the 1 K pull-up resistor.
JTAG_TCK/
M3_TCK
1
Input No Microsemi
recommends
TCK to be tied to
VSS or VDDI
through a resistor
on the board
when unused.
This is according
to IEEE 1532
requirements.
Clock input to JTAG controller and UJTAG
2
.
If JTAG is not used, Microsemi recommends tying it off. The
tied off resistor must be placed close to the FPGA pin. This
prevents creation of totem-pole current due to random
oscillations on the input buffer and operation if TMS enters
an undesired state.
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