Microsemi IGLOO2 - Auto Update

Auto Update
UG0451 User Guide Revision 7.0 35
8 Auto Update
In auto update programming mode, a device is auto programmed with an update image on power up.
The update image is stored in an external flash connected to the MSS/HPMS SPI_0 port of the device.
The design version of the update image must be greater than the image version already programmed in
the device.
When auto update is enabled, SmartFusion2/IGLOO2 MSS/HPMS SPI_0 can be configured to share the
SPI_0 pin with an SPI controller implemented in the FPGA fabric. To share the SPI_0 port, a multiplexer
needs to be implemented in the FPGA fabric to switch the SPI_0 pins between MSS/HPMS SPI_0 and
the fabric SPI controller. For more information, see DG0636: Implementing Auto Update and
Programming Recovery Features (Using Ethernet Interface) for SmartFusion2 Devices Demo Guide.
Auto update is not supported in M2S/M2GL050 devices.
Figure 18 • Auto Update Programming Ports
Auto update mode needs to be turned on in Libero SoC (see Configuring the Device for Auto Update,
page 36), and the device needs to be programmed first with the exported bitstream. The SPI flash can be
preprogrammed and installed on the board or it can be programmed remotely using the update image
and the SPI directory. The FPGA can be programmed with only one update image version at a time.
Every time auto update of a new update image is desired
• the SPI flash needs to be reprogrammed with that new update image.
• the SPI directory corresponding to the new update image needs to be programmed into the SPI
flash before starting the auto update.
During auto update, the system controller reads the version and address of the image from the SPI
directory and programs the device with the update image if it is a higher version of the image already
programmed in the FPGA.
If auto update is enabled, and the SPI flash is blank or does not contain the SPI directory, the device
attempts auto update but fails bitstream authentication and aborts programming. However, the state of
FPGA Fabric
Micro SRAM
(64x18)
Micro SRAM
(64x18)
Large SRAM
(1024x18)
Large SRAM
(1024x18)
Math Block
MACC (18x18)
Math Block
MACC (18x18)
DDR
Bridge
MSS
DDR Controller
+ PHY
Instruction
Cache
eSRAM
TSE MAC HPDMAFIC_1FIC_0COMM_BLK
SYSREG eNVM
HS USB
OTG ULPI
PDMAAPB
SRAM-PUF
JTAG I/O
DDR User I/O
SPI I/O
Multi-Standard User I/O (MISO)
SHA256
AES256
In-Application
Programming
NRBGECC
Flash*Freeze
FIIC
RTC
WDT
CAN
SPI x 2
MMUART x 2
I
2
C x 2
Timer x 2
AHB Bus Matrix (ABM)
MPU
ARM
®
Cortex
™
-M3
Microcontroller
Subsystem (MSS)
System Controller
ETM
S
D
AHB
SMC_FIC AXI/AHBConfig
AHB AHBInterupts
I
FP
G
A Fabric
Mic
ro
a
ndard User I
/O
(
MI
SO)
Multi-Standard User I/O (MISO)
Standard Cell /
SEU Immune
Flash Based /
SEU Immune
Remote Update
Update Image
Versions
MSS SPI_0 Port
SPI Flash
Vn
.
.
.
.
.
.
V2
V1
FLASH_GOLDEN_N Pin
DEVEREST_N Pin