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3 DATA COMMUNICATION USING NONPROCEDURAL PROTOCOL
3.1 Receiving Data from Target Device
Receive data arrangement
The following explains the data arrangement when data received from a target device is stored to the receive area.
• The received message is stored to the C24 buffer memory (Receive data storage area).
• The data is stored to the receive data storage area in the order of data reception from (L)(H) of the low address to
(L)(H) of the next address.
Under the following conditions, when the receive end data quantity is an odd byte, 00H is stored in the upper byte of the last
data storage position:
When the unit for the receive end data quantity is designated in bytes.
When data reception is performed using the receive end code.
When receive data "ABCDEFG123" was stored (The receive area is the default value.)
*1 The OS area of C24 is the memory (8448 bytes) that temporarily stores the data to be received while a reception data read request is
being issued to the CPU module. (Reading received data in the OS area cannot be performed by the user.)
When the program finishes reading the received data in the buffer memory in response to the current read request, the received data in
the OS area, and any succeeding received data, is stored successively in the receive area in the buffer memory when the next read
request is issued.
Also, when the free OS area, which stores the received data, is reduced to 64 bytes (default value) or less, a request to discontinue data
transmission from the target device is issued by the following transmission control (The RS (RTS) signal does not turn OFF):
When DTR control is set, the ER(DTR) signal turns OFF.
When DC1/DC3 control is set, DC3 is sent.
When there is no more free OS area to store received data, SIO error occurs and the SIO information bit of the 'CH side LED lighting
status and communication error status' (Un\G513/514) turns ON. In that case, succeeding received data is discarded until a free area
becomes available in the OS area.
For more details on the transmission control, refer to the following section.
Page 236 DATA COMMUNICATIONS USING DC CODE TRANSMISSION CONTROL
(B)
42H
(C)(D)
44H
(E)(F)
(G)(1)
(2)(3)
(A)
"321GFEDCBA"
46H
31H
33H 23H
47H
45H
43H
41H
(*1)
C24
CH1
address
Buffer memory
Receive data count storage area
5 or 10
Head
OS area
Received data storage area
The received data are stored
in the order of low address (L)→(H),
next address (L)→(H)
as they were received.
Target device
Un\G
1536
Un\G
1537
Un\G
1538
Un\G
1539
Un\G
1540
Un\G
1541
Un\G
1542
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