Mitsubishi QJ71C24N - Clearing the Programmable Controller CPU Information

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MELSEC-Q
11 TROUBLESHOOTING
11.1.7 Clearing the programmable controller CPU information
This section explains how to clear the programmable controller CPU information.
(1) Programmable controller CPU information
(a) This is information about the access target CPU type used in MC protocol
communications.
The Q series C24 obtains this information from the access target CPU at the
time of initial access, and stores it inside the Q series C24.
Since access is made based on this information, the processing speed will
be increased from the second access.
(b) The programmable controller CPU information is cleared in the following
cases:
• When the programmable controller is powered OFF and then ON, or when
the CPU module is reset
• When the programmable controller CPU information clear request is
executed
(2) If the programmable controller CPU information has not been
correctly obtained
The following problems may occur:
• Accessible device range is narrowed. (Error code: 7140
H)
• Some of commands and/or devices cannot be used. (Error code: 7142
H,
714D
H), etc.
In the above case, execute the programmable controller CPU information clear
request.
POINT
If initial access is made at startup of the access target CPU or while the network is
unstable, the programmable controller CPU information may not be correctly
acquired.
(3) Operation of the programmable controller CPU information clear
request
(a) Write "4C43H" to the programmable controller CPU information clear request
(address: 80
H). (Set by the user)
b15 b0
80
H
Write 4C43H
0000
H
: No request (Set by Q series C24)
4C43
H: Requested
Buffer memory address
to
(Default: 0000
H)
(b) The programmable controller CPU information clear processing of the Q series
C24 is executed.
1
(c) Upon completion of the clear processing, "0000
H" is written to the
programmable controller CPU information clear request (address: 80
H). (Set
by the Q series C24)
0000
H
4C43
H
0000
H
Clear request
Buffer memory address: 80
H
Clear processing
1 The transmission sequence status (address: 255H/265H) is also initialized.