Motorola M68000 - ShiftRotate Instruction Execution Times

7- 6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
Table 7-7. Single Operand Instruction
Execution Times
Instruction Size Register Memory
CLR Byte
Word
Long
8(2/0)
8(2/0)
10(2/0)
12(2/1)+
16(2/2)+
24(2/4)+
NBCD Byte 10(2/0) 12(2/1)+
NEG Byte
Word
Long
8(2/0)
8(2/0)
10(2/0)
12(2/1)+
16(2/2)+
24(2/4)+
NEGX Byte
Word
Long
8(2/0)
8(2/0)
10(2/0)
12(2/1)+
16(2/2)+
24(2/4)+
NOT Byte
Word
Long
8(2/0)
8(2/0)
10(2/0)
12(2/1)+
16(2/2)+
24(2/4)+
Scc Byte, False
Byte, True
8(2/0)
10(2/0)
12(2/1)+
12(2/1)+
TAS Byte 8(2/0) 14(2/1)+
TST Byte
Word
Long
8(2/0)
8(2/0)
8(2/0)
8(2/0)+
8(2/0)+
8(2/0)+
+Add effective address calculation time.
7.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES
Table 7-8 lists the timing data for the shift and rotate instructions. The total number of
clock periods, the number of read cycles, and the number of write cycles are shown in the
previously described format. The number of clock periods, the number of read cycles, and
the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
Table 7-8. Shift/Rotate Instruction Execution Times
Instruction Size Register Memory
ASR, ASL Byte
Word
Long
10+2n(2/0)
10+2n(2/0)
12+n2(2/0)
—
16(2/2)+
—
LSR, LSL Byte
Word
Long
10+2n(2/0)
10+2n(2/0)
12+n2(2/0)
—
16(2/2)+
—
ROR, ROL Byte
Word
Long
10+2n(2/0)
10+2n(2/0)
12+n2(2/0)
—
16(2/2)+
—
ROXR, ROXL Byte
Word
Long
10+2n(2/0)
10+2n(2/0)
12+n2(2/0)
—
16(2/2)+
—
+Add effective address calculation time for word operands.
n is the shift count.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...