MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 7- 7
7.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES
Table 7-9 lists the timing data for the bit manipulation instructions. The total number of
clock periods, the number of read cycles, and the number of write cycles are shown in the
previously described format. The number of clock periods, the number of read cycles, and
the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
Table 7-9. Bit Manipulation Instruction Execution Times
Dynamic Static
Instruction Size Register Memory Register Memory
BCHG Byte
Long
—
12(2/0)*
12(2/1)+
—
—
20(4/0)*
20(4/1)+
—
BCLR Byte
Long
—
14(2/0)*
12(2/1)+
—
—
22(4/0)*
20(4/1)+
—
BSET Byte
Long
—
12(2/0)*
12(2/1)+
—
—
20(4/0)*
20(4/1)+
—
BTST Byte
Long
—
10(2/0)
8(2/0)+ —
18(4/0)
16(4/0)+
—
+Add effective address calculation time.
* Indicates maximum value; data addressing mode only.
7.8 CONDITIONAL INSTRUCTION EXECUTION TIMES
Table 7-10 lists the timing data for the conditional instructions. The total number of clock
periods, the number of read cycles, and the number of write cycles are shown in the
previously described format. The number of clock periods, the number of read cycles, and
the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
Table 7-10. Conditional Instruction Execution Times
Instruction Displacement
Trap or Branch
Taken
Trap or Branch
Not Taken
Bcc Byte
Word
18(4/0)
18(4/0)
12(2/0)
20(4/0)
BRA Byte
Word
18(4/0)
18(4/0)
—
—
BSR Byte
Word
34(4/4)
34(4/4)
—
—
DBcc CC True
CC False
—
18(4/0)
20(4/0)
26(6/0)
CHK — 68(8/6)+* 14(2/0)
TRAP — 62(8/6) —
TRAPV — 66(10/6) 8(2/0)
+Add effective address calculation time for word operand.
* Indicates maximum base value.
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cale Semiconductor,
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