Motorola M68000 - 3.4 BUS ARBITRATION CONTROL

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 3- 5
Table 3-1. Data Strobe Control of Data Bus
UDS L DS
R/
W
D8–D15 D0–D7
High High — No Valid Data No Valid Data
Low Low High Valid Data Bits
15–8
Valid Data Bits
7–0
High Low High No Valid Data Valid Data Bits
7–0
Low High High Valid Data Bus
15–8
No Valid Data
Low Low Low Valid Data Bits
15–8
Valid Data Bits
7–0
High Low Low Valid Data Bits
7–0*
Valid Data Bits
7–0
Low High Low Valid Data Bits
15–8
Valid Data Bits
15–8*
*These conditions are a result of current implementation and may not appear
on future devices.
Data Strobe (
DS
) (MC68008)
This three-state signal and R/W control the flow of data on the data bus of the
MC68008. Table 3-2 lists the combinations of these signals and the corresponding data
on the bus. When the R/W line is high, the processor reads from the data bus. When
the R/W line is low, the processor drives the data bus.
Table 3-2. Data Strobe Control
of Data Bus (MC68008)
DS
R/
W
D0–D7
1 — No Valid Data
0 1 Valid Data Bits 7–0 (Read Cycle)
0 0 Valid Data Bits 7–0 (Write Cycle)
Data Transfer Acknowledge (
DTACK
).
This input signal indicates the completion of the data transfer. When the processor
recognizes DTACK during a read cycle, data is latched, and the bus cycle is terminated.
When DTACK is recognized during a write cycle, the bus cycle is terminated.
3.4 BUS ARBITRATION CONTROL
The bus request, bus grant, and bus grant acknowledge signals form a bus arbitration
circuit to determine which device becomes the bus master device. In the 48-pin version of
the MC68008 and MC68EC000, no pin is available for the bus grant acknowledge signal;
this microprocessor uses a two-wire bus arbitration scheme. All M68000 processors can
use two-wire bus arbitration.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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