Neoway N58 - Page 25

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N58 Hardware User Guide

Chapter 4 Module Pins

SPI interface

SPI_CLK

Clock signal

Leave this pin floating

if it is not used.

SPI_MISO

Output from

the slave

device, and

input from

the master

device

Leave this pin floating

if it is not used.

SPI_MOSI

Input from

the slave

device, and

output from

the master

device

Leave this pin floating

if it is not used.

SPI_CS_N

Chip select

signal of the

slave device

Leave this pin floating

if it is not used.

GPIO interface

GPIO_0

GPIO

Leave this pin floating

if it is not used.

GPIO_2

GPIO

Leave this pin floating

if it is not used.

GPIO_3

GPIO

Leave this pin floating

if it is not used.

Audio SPK interface

SPK_P

Speaker

output

positive

SPK_N

Speaker

output

negative

Audio MIC interface

MIC_P

Microphone

input

positive

MIC_N

Microphone

input

negative

Main Page

Table of Contents3
About this Document8
Scope8
Audience8
Change History8
Conventions10
Related Documents11
Safety Recommendations12
About N5813
Product Overview13
Table 2-1 Variants and Frequency Bands Supported13
Block Diagram14
Figure 2-1 Block Diagram14
Basic Features15
Reference Standards17
Module Pins18
Pin Layout18
Figure 4-1 Pin Layout of the N58 Module (Top View)18
Pin Description19
Table 4-1 IO Type Description and DC Characteristics19
Table 4-2 Pin Description19
Application Interfaces28
Power Interface28
Vbat28
Figure 5-1 Voltage Drop of the Power Supply29
Figure 5-2 Recommended Design 129
Figure 5-3 Recommended Design 230
Figure 5-4 Recommended Design 331
Figure 5-5 Recommended Design 431
Vdd_1P833
Control Interface33
Pwrkey_N33
Figure 5-6 Reference Design of Module Startup Controlled by Button34
Figure 5-7 Reference Design of Module Startup Controlled by MCU34
Figure 5-8 Reference Design of Automatic Startup Once Powered on35
Figure 5-9 Startup Process36
Figure 5-10 Hard Shutdown Process36
Reset_N37
Figure 5-11 Module Reset Controlled by Button37
Figure 5-12 Reference Reset Circuit in Which a Triode Is Used for Isolation37
Sleep38
Figure 5-13 Reset Process of the N58 Module38
Figure 5-14 Process of Entering the Sleep Mode39
Figure 5-15 Process of Call Service Processing in Sleep Mode39
Figure 5-16 Process of Exiting from the Sleep Mode40
Peripheral Interface41
Usb41
Figure 5-17 Reference Design of the Module Sleep and Wake-Up Control Circuit41
Figure 5-18 Reference Design of the USB Connection Circuit42
Uart43
Figure 5-19 Reference Design of UART Connections44
Figure 5-20 Recommended Level Shifting Circuit 144
Figure 5-21 Recommended Level Shifting Circuit 245
Usim46
Figure 5-22 Recommended Level Shifting Circuit 346
Figure 5-23 Reference Design of USIM Card (with the Hot Plug Function) Interfaces47
Figure 5-24 Reference Design of USIM Card (Without the Hot Plug Function) Interfaces48
Sdio49
Figure 5-25 SDIO Reference Design49
Spi50
I2C51
Figure 5-26 SPI Reference Design51
Figure 5-27 I2C Reference Design51
Audio Interfaces52
Analog Audio Input Interfaces52
Figure 5-28 Reference Design of Differential MIC Input52
Analog Audio Output Interfaces53
Figure 5-29 Reference Design of the Built-In Power Amplifier53
Figure 5-30 Reference Design of the External Power Amplifier54
Video Interfaces55
Lcd55
Table 5-1 Description of LCD Function Pins55
Camera56
Other Interfaces56
Adc56
Net_Light56
Table 5-2 Description of Camera Function Pins56
Ring57
Figure 5-31 Reference Design of Driving an LED Indicator by Controlling a Triode57
Usb_Boot58
Figure 5-32 RING Prompt for an Incoming Voice Call58
Figure 5-33 RING Prompt for an SMS Message58
VBACKUP and VRTC59
Figure 5-34 Reference Design of Forcible Download59
Gpio60
Gnss_Lna_En60
Figure 5-35 Reference Design of VBACKUP and VRTC Power Supply60
Keypad61
Figure 5-36 Keypad Reference Design61
1Pps62
Vcc_Gnss_Bias62
Figure 5-37 1PPS Output Waveform62
RF Interfaces63
ANT_MAIN Antenna Interface63
Figure 5-38 Reference Design of GNSS Active Antenna Power Supply and Detection Circuit63
Figure 5-39 L-Type Matching Network64
Figure 5-40 T-Type Matching Network64
Figure 5-41 Π-Type Matching Network64
ANT_GNSS Interface65
Figure 5-42 Recommended RF PCB Design65
Figure 5-43 GNSS Structure Inside the Module66
Figure 5-44 Reference Design of an Active GNSS Antenna67
ANT_BT Interface68
Antenna Assembly68
Figure 5-45 Reference Design of a Passive GNSS Antenna68
Figure 5-46 Package Specifications of Murata's GSC RF Connector69
Figure 5-47 Module RF Connection Method69
Figure 5-48 Antenna Layout Example70
Figure 5-49 Layout Around the Antenna70
Electrical Characteristics and Reliability71
Electrical Characteristics71
Table 6-1 Electrical Characteristics of the N58 Module71
Table 6-2 Current Consumption of the N58 Module (Typical)71
Temperature Characteristics72
ESD Protection Characteristics72
Table 6-3 ESD Protection Characteristics72
RF Characteristics73
Operating Bands73
Table 7-1 Operating Bands of the N58 Module73
TX Power and RX Sensitivity74
Table 7-2 RF TX Power of the N58 Module74
Table 7-3 RF RX Sensitivity of the N58 Module74
GNSS Parameters75
Table 7-4 GNSS Parameters75
WLAN/BT Characteristics76
Table 7-5 WLAN/BT TX Power and RX Sensitivity76
Mechanical Characteristics77
Dimensions77
Figure 8-1 N58 Top and Side Dimensions (Unit: MM)77
Label78
Packaging78
Figure 8-2 N58 Label Examples78
Reel and Tape79
Moisture80
Assembly81
Module PCB Package81
Figure 9-1 Bottom View of the N58 Module PCB Package (Unit: MM)81
Application PCB Package82
Stencil82
Figure 9-2 Top View of the Recommended N58 Application PCB Package (Unit: MM)82
Solder Paste83
SMT Furnace Temperature Curve83
Figure 9-3 SMT Furnace Temperature Curve83
Abbreviations85

Neoway N58 - Page 25

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