Hardware description
4.11 NFC antenna interface
The nRF5340 DK supports an NFC tag.
NFC-A Listen Mode operation is supported on the nRF5340 SoC. The NFC antenna input is available on
connector J5 on the nRF5340 DK.
Figure 32: NFC antenna connector
NFC uses two pins, NFC1 and NFC2, to connect the antenna. These pins are shared with GPIOs (P0.02
and P0.03). The PROTECT field of the NFCPINS register in User Information Configuration Registers (UICR)
defines the usage of these pins and their protection level against abnormal voltages. The content of the
NFCPINS register is reloaded at every reset.
Configuring NFC pins as GPIOs
The NFC pins are enabled by default. NFC can be disabled and GPIOs enabled by setting the
CONFIG_NFCT_PINS_AS_GPIOS to y. See Configuring your application for instructions.
Pins P0.02/NFC1 and P0.03/NFC2 are by default configured to use the NFC antenna. To use these
pins as GPIO, R43 and R46 must be not connected (NC) and R42 and R45 must be shorted with an OR
resistor.
D14
D15
D16
D17
D18
D19
D20
D21
GPIO_IF3
GPIO_IF3
P0.01
P0.00
P0.07/AIN3
P0.08/TRACEDATA3
P0.09/TRACEDATA2
P0.10/TRACEDATA1
R42
N.C.
R45
N.C.
P0.03/NFC2
P0.02/NFC1
R46
0R
R43
0R
C43
300pF
C44
300pF
NFC1
NFC2P0.03/NFC2
P0.02/NFC1
Figure 33: NFC input
4.12 Extra op-amp
The voltage follower for the power supply uses a dual package Operational Amplifier (op-amp).
The extra op-amp is routed out to a connector (P28, not mounted) so that it is accessible for the user.
For more information on the power supply, see Power supply on page 12.
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