Nvidia JETSON TX2 - Page 31

NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 31
Termination
50

To GND Single Ended for P & N
Impedance
Trace Impedance differential / Single Ended
85 / 50

±15%. See note 1
Reference plane
GND
Spacing
Trace Spacing (Stripline/Microstrip) Pair  Pair
To plane & capacitor pad
To unrelated high-speed signals
3x / 4x
3x / 4x
3x / 4x
Dielectric
Length/Skew
Trace loss characteristic @ 2.5GHz
< 0.7
dB/in
The following max length is derived based on this
characteristic. See note 3
Breakout region (Max Length)
41.9
ps
Minimum width and spacing. 4x or wider
dielectric height spacing is preferred
Max trace length
5.5 (880)
in (ps)
Max PCB via distance from the BGA
41.9
ps
Max distance from BGA ball to first PCB via.
PCB within pair (intra-pair) skew
0.15 (0.5)
mm (ps)
Do trace length matching before hitting
discontinuities
Within pair (intra-pair) matching between
subsequent discontinuities
0.15 (0.5)
mm (ps)
Differential pair uncoupled length
41.9
ps
Via
Via placement
Place GND vias as symmetrically as possible to data pair vias. GND via distance should be placed
less than 1x the diff pair via pitch
Max # of Vias PTH Vias
Micro-Vias
2 for TX traces & 2 for RX trace
No requirement
Max Via stub length
0.4
mm
Longer via stubs would require review
Routing signals over antipads
Not allowed
AC Cap
Value Min/Max
0.075 / 0.2
uF
Only required for TX pair when routed to connector
Location (max length to adjacent discontinuity)
8
mm
Discontinuity such as edge finger, component pad
Voiding
Voiding the plane directly under the pad 3-4
mils larger than the pad size is
recommended.
Serpentine
Min bend angle
135
deg (a)
S1 must be taken care in
order to consider Xtalk to
adjacent pair
Dimension Min A Spacing
Min B, C Length
Min Jog Width
4x
1.5x
3x
Trace width
MIsc.
Routing signals over antipads
Not allowed
Routing over voids
When signal pair approaches Vias, the maximal trace length across the void on the plane is 50mil.
Connector
Voiding
Voiding the plane directly under the pad 5.7
mils larger than the pad size is
recommended.
Keep critical PCIe traces such as PEX_TX/RX, TERMP etc. away from other signal traces or unrelated power traces/areas or powe r supply components
Note:
1. The PCIe spec. has 40-60 absolute min/max trace impedance, which can be used instead of the 50 , ± 15%.
2. If routing in the same layer is necessary, route group TX & RX separately without mixing RX/TX routes & keep distance
between nearest TX/RX trace & RX to other signals 3x RX-RX separation.
3. Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the
max trace lengths will need to be reduced.
4. Do length matching before Via transitions to different layers or any discontinuity to minimize common mode conversion.