EasyManua.ls Logo

Nvidia JETSON TX2 - Page 80

Nvidia JETSON TX2
103 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 80
PEX1_RX+/-
๎ฅด
0.1uF capacitors if directly connected
PEX2_RX+/-
๎ฅด
0.1uF capacitors if directly connected
PEX_RFU_RX+/-
๎ฅด
0.1uF capacitors
SATA_TX+/-
๎ฅด
0.01uF capacitors
SATA_RX+/-
๎ฅด
0.01uF capacitors
SATA_DEV_SLP
๎ฅด
1.8V to 3.3V Level Shifter
Ethernet
GBE_MDI0+/-
๎ฅด
Magnetics near RJ45 connector
GBE_MDI1+/-
๎ฅด
Magnetics near RJ45 connector
GBE_MDI2+/-
๎ฅด
Magnetics near RJ45 connector
GBE_MDI3+/-
๎ฅด
Magnetics near RJ45 connector
GBE_LINK100#
๎ฅด
LED and pull-up Current Limiting Circuit
GBE_LINK1000#
๎ฅด
LED and pull-up Current Limiting Circuit
GBE_LINK_ACT#
๎ฅด
LED and pull-up Current Limiting Circuit
DP[1:0] for eDP/DP
DPx_TX3+/-
๎ฅด
0.1uF capacitors
DPx_TX2+/-
๎ฅด
0.1uF capacitors
DPx_TX1+/-
๎ฅด
0.1uF capacitors
DPx_TX0+/-
๎ฅด
0.1uF capacitors
DPx_AUX_CH+
๎งญ๎งฌ๎งฌ๎ฌ๎ก๎˜ƒ๎™—๎žต๎ฏ๎ฏ-down to GND near connector
(DP only)
0.1uF capacitor
DPx_AUX_CH-
100k๎ก๎˜ƒ๎™—๎žต๎ฏ๎ฏ-up to 3.3V near connector (DP
only)
0.1uF capacitor
DPx_HPD
10k๎ก๎˜ƒ๎™—๎žต๎ฏ๎ฏ-up to 1.8V near main conn. &
๎งญ๎งฌ๎งฌ๎ฌ๎ก๎˜ƒ๎™—๎žต๎ฏ๎ฏ-down to GND on DP side of
level shifter.
Level Shifter (w/output toward main
connector) near main connector & 100k๎ก๎˜ƒ
resistor to DP connector. Level shifter must be
non-inverting.
DP[1:0] for HDMI
DPx_TX3+/-
499๎ก๎ฅ•๎˜ƒ๎งญ๎จน๎˜ƒ๎žŒ๎œž๎ž๎๎ž๎žš๎ฝ๎žŒ๎˜ƒ ๎žš๎ฝ๎˜ƒ๎งฒ๎งฌ๎งฌ๎ก๎˜ƒ๎œ๎œž๎œ‚๎œš๎˜ƒ๎žš๎ฝ๎˜ƒGND
0.1uF capacitors
DPx_TX2+/-
499๎ก๎ฅ•๎˜ƒ๎งญ๎จน๎˜ƒ๎žŒ๎œž๎ž๎๎ž๎žš๎ฝ๎žŒ๎˜ƒ ๎žš๎ฝ๎˜ƒ๎งฒ๎งฌ๎งฌ๎ก๎˜ƒ๎œ๎œž๎œ‚๎œš๎˜ƒ๎žš๎ฝ๎˜ƒGND
0.1uF capacitors
DPx_TX1+/-
499๎ก๎ฅ•๎˜ƒ๎งญ๎จน๎˜ƒ๎žŒ๎œž๎ž๎๎ž๎žš๎ฝ๎žŒ๎˜ƒ ๎žš๎ฝ๎˜ƒ๎งฒ๎งฌ๎งฌ๎ก๎˜ƒ๎œ๎œž๎œ‚๎œš๎˜ƒ๎žš๎ฝ๎˜ƒGND
0.1uF capacitors
DPx_TX0+/-
499๎ก๎ฅ•๎˜ƒ๎งญ๎จน๎˜ƒ๎žŒ๎œž๎ž๎๎ž๎žš๎ฝ๎žŒ๎˜ƒ ๎žš๎ฝ๎˜ƒ๎งฒ๎งฌ๎งฌ๎ก๎˜ƒ๎œ๎œž๎œ‚๎œš๎˜ƒ๎žš๎ฝ๎˜ƒGND
0.1uF capacitors
DPx_AUX_CH+/-
10k๎ก๎˜ƒ๎™—๎žต๎ฏ๎ฏ-up to 3.3V near main conn. &
๎งญ๎ฅ˜๎งด๎ฌ๎ก๎˜ƒ๎™—๎žต๎ฏ๎ฏ-up to 5V near HDMI conn.
Bidirectional level shifter between Pull-ups in
Parallel Termination column
DPx_HPD
10k๎ก๎˜ƒ๎™—๎žต๎ฏ๎ฏ-up to 1.8V near main conn. &
๎งญ๎งฌ๎งฌ๎ฌ๎ก๎˜ƒ๎™—๎žต๎ฏ๎ฏ-down to GND near HDMI conn.
Level shifter (w/output toward main connector)
between Pull-up & Pull-down in Parallel
Termination column. Level shifter can be
inverting or non-inverting. ๎งญ๎งฌ๎งฌ๎ฌ๎ก๎˜ƒ๎ž๎œž๎žŒ๎๎œž๎ž๎˜ƒ
resistor between pull-down & HDMI connector.
Power
Module Power Supplies
Supply (Carrier Board)
Usage
(V)
Supply Type
Source
Enable
VDD_IN
Main Supply from Adapter
TX2: 5.5-
19.6
TX2i:
9.0-19.0
Adapter
na
na
VDD_RTC
Real-time clock supply
1.65-5.5
PMIC is supply
when charging
cap or coin cell
Super cap or coin
cell is source when
system power
removed
na
Carrier Board Supplies
VDD_MUX
Main power input from DC
Adapter
TX2: 5.5-
19.6
TX2i:
9.0-19.0
FETs
DC Adapter
VDD_5V0_IO_SYS
Main 5V supply
5.0
DC/DC
VDD_MUX
CARRIER_PWR_ON
VDD_3V3_SYS
Main 3.3V supply
3.3
DC/DC
VDD_MUX
3V3_SYS_BUCK_EN
VDD_1V8
Main 1.8V supply
1.8
DC/DC
VDD_5V0_IO_SYS
1V8_IO_VREG_EN
(VDD_3V3_SYS_PG)
VDD_3V3_SLP
3.3V rail, off in Sleep (various)
3.3
FETs/Load
Switch
VDD_3V3_SYS
SOC_PWR_REQ

Other manuals for Nvidia JETSON TX2

Related product manuals