Nvidia JETSON TX2 - Page 96

NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 96
Pin #
Module Pin Name
Tegra Signal
Usage/Description
Usage on the Carrier
Board
Direction
Pin Type
A47
RESET_IN#
(PMIC NRST_IO)
Reset In. System Reset driven from
PMIC to carrier board for devices
requiring full system reset. Also driven
from carrier board to initiate full system
reset (i.e. RESET button). A pull-up is
present on module.
Bidir
Open Drain, 1.8V
A48
CARRIER_PWR_ON

Carrier Power On. Used as part of the
power up sequence. The module asserts
this signal when it is safe for the carrier
-up to
VDD_3V3_SYS is present on the module.
Output
Open-Collector  3.3V
A49
CHARGER_PRSNT#
(PMIC ACOK)
Charger Present. Connected on module

-up
internally to MBATT (VDD_5V0_SYS).
Can optionally be used to support auto-
power-on where the module platform
will power-on when the main power
source is connected instead of waiting
for a power button press.
Input
MBATT level  5.0V (see
note 3)
A50
VDD_RTC
(PMIC BBATT)
Real-Time-Clock. Optionally used to
provide back-up power for RTC.
Connects to Lithium Cell or super
capacitor on Carrier Board. PMIC is
supply when charging cap or coin cell.
Super cap or coin cell is source when
system is disconnected from power.
Battery Back-up using
Super-capacitor
Bidir
1.65V-5.5V
B1
VDD_IN

Main power  Supplies PMIC & external
supplies
Main DC input
Input
5.5V-19.6V (TX2)
9.0V-19.0V (TX2i)
B2
VDD_IN
B3
GND

GND
GND

GND
B4
GND

GND
GND

GND
B5
RSVD

Not used



B6
I2C_PM_DAT
GEN8_I2C_SDA
PM I2C Data
I2C (General)
Bidir
Open Drain  1.8V
B7
CARRIER_STBY#
SOC_PWR_REQ
Carrier Board Standby: The module
drives this signal low when it is in the
standby power state.
System
Output
CMOS  1.8V
B8
VIN_PWR_BAD#

VDD_IN Power Bad. Carrier board
indication to the module that the
VDD_IN power is not valid. Carrier board
should de-assert this (drive high) only
when VDD_IN has reached its required
voltage level and is stable. This prevents
Tegra from powering up until the
VDD_IN power is stable.
Input
CMOS  5.0V
B9
GPIO17_MDM2AP_READY
GPIO_PQ7
Modem to AP (Tegra) Ready or GPIO
M.2 Key E
Input
CMOS  1.8V
B10
GPIO18_MDM_COLDBOOT
GPIO_PQ6
Modem Coldboot or GPIO
Input
CMOS  1.8V
B11
JTAG_TCK
JTAG_TCK
JTAG Test Clock
JTAG Header & Debug
Connector
Input
CMOS  1.8V
B12
JTAG_TDI
JTAG_TDI
JTAG Test Data In
Input
CMOS  1.8V
B13
JTAG_GP0
JTAG_TRST_N
JTAG General Purpose 0 (Test Reset)
Input
CMOS  1.8V
B14
GND

GND
GND

GND
B15
UART2_RX
UART2_RX
UART 2 Receive
M.2 Key E
Input
CMOS  1.8V
B16
UART2_TX
UART2_TX
UART 2 Transmit
Output
CMOS  1.8V
B17
FAN_TACH
UART5_TX
Fan Tachometer
Fan
Input
CMOS  1.8V
B18
RSVD

Not used



B19
GPIO11_AP_WAKE_BT
GPIO_PQ5
AP (Tegra) Wake Bluetooth or GPIO
Display Connector
Output
CMOS  1.8V
B20
GPIO10_WIFI_WAKE_AP
GPIO_WAN4
WLAN 2 Wake AP (Tegra) or GPIO
M.2 Key E
Input
CMOS  1.8V
B21
GPIO12_BT_EN
MCU_PWR_REQ
BT 2 Enable or GPIO
Output
CMOS  1.8V
B22
GPIO13_BT_WAKE_AP
GPIO_WAN2
BT 2 Wake AP (Tegra) or GPIO
Input
CMOS  1.8V
B23
GPIO7_TOUCH_RST
SAFE_STATE
Touch Reset or GPIO
Display Connector
Output
CMOS  1.8V
B24
TOUCH_CLK
TOUCH_CLK
Touch Clock
Output
CMOS  1.8V
B25
GPIO6_TOUCH_INT
CAN_GPIO7
Touch Interrupt or GPIO
Input
CMOS  1.8V
B26
LCD_VDD_EN
GPIO_EDP0
Display VDD Enable
Output
CMOS  1.8V
B27
LCD0_BKLT_PWM
GPIO_DIS0
Display Backlight PWM 0
Output
CMOS  1.8V
B28
LCD_BKLT_EN
GPIO_DIS3
Display Backlight Enable
Output
CMOS  1.8V
B29
SDIO_CMD
SDMMC3_CMD
SDIO Command
SDIO
Bidir
CMOS  1.8V
B30
SDIO_CLK
SDMMC3_CLK
SDIO Clock
Output
CMOS  1.8V
B31
GND

GND
GND

GND