NXP Semiconductors FS4500 - Page 33

NXP Semiconductors FS4500/FS6500 evaluation boards
KTFRDMFS4500-FS6500EVMUG
FS4500/FS6500 evaluation boards All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
User guide Rev. 4.0 — 12 June 2017
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Tables
Tab. 1. EVMs supporting the FS45xx/FS65xx family .....5
Tab. 2. FS45xx/FS65xxfeatures .................................... 7
Tab. 3. Board description .............................................. 8
Tab. 4. LEDs ..................................................................9
Tab. 5. Jumper definitions ........................................... 10
Tab. 6. Test point definitions ....................................... 11
Tab. 7. VBAT Phoenix connector (J1) .........................12
Tab. 8. SPI connector (J2_FRDM) .............................. 12
Tab. 9. CAN & LINconnector (J3) ............................... 13
Tab. 10. USB connector (J33) .......................................13
Tab. 11. I/O connector (J1_FRDM) ............................... 14
Tab. 12. Power supply connector (J2) ...........................14
Tab. 13. KL25Z Analog regulator inputs (J10_FRDM) ... 15
Tab. 14. SW1 .................................................................16
Tab. 15. Use case register configuration Excel file
example ...........................................................25
Figures
Fig. 1. FRDMFS6523CAEVM .......................................1
Fig. 2. FRDMFS65/FRDMFS45 block diagram ............ 6
Fig. 3. Evaluation board description .............................8
Fig. 4. LEDs ..................................................................9
Fig. 5. Jumpers ...........................................................10
Fig. 6. Test points .......................................................11
Fig. 7. Connectors ...................................................... 12
Fig. 8. Switches .......................................................... 16
Fig. 9. VCCA and VAUX voltage settings ...................17
Fig. 10. VAUX regulator ............................................... 17
Fig. 11. VCORE configuration ...................................... 18
Fig. 12. FCRBM Resistor Bridge ..................................19
Fig. 13. Evaluation board hardware configuration ........ 21
Fig. 14. Software overview ...........................................22