8 OPAL-RT Technologies OP4200 User Manual
DESCRIPTION
System Interconnection Details
SYSTEM INTERCONNECTION DETAILS
Two SFP sockets are located on the left side if the chassis to allow interconnexion with 3rd-party
devices or with other OPAL-RT chassis. These sockets are connected to the PL section of the Zynq
module and configured by the FPGA programming file (generated using OPAL-RT RT-XSG toolbox).
There are two standard modes of operation available for the SFP ports, both based on the Xilinx Aurora
communication protocol:
• Generic Aurora communication: this mode is enabled using the RT-XSG blockset’s Generic Aurora
blocks in the FPGA programming file’s Simulink model. These blocks are used to exchange
data with 3rd-party devices or with other OPAL-RT systems The data communication layer (data
packing/unpacking) must be configured by the user according to the targeted application. The
communication speed is configurable between 1 and 5 GBps and the SFP transceivers should be
selected accordingly.
• OPAL-RT MUlti-System Expansion link (MUSE)
1
: this mode encapsulates the Aurora protocol within
a network protocol designed by OPAL-RT for inter-system communication. The communication
speed is set to 5Gbps by default, but downgrades automatically to the speed of the other port, if
that port is used at a lower speed for 3rd party device connection.
The MUSE mode is selected in the RT-XSG block by setting the synthesis manager architecture
option to <remote>. In this mode, the unit must be connected to another OPAL-RT system that is
connected in ‘central’ mode, and it then becomes a remote expansion unit (similar to an OP4520 or
OP5607). The simulator ARM CPUs are then used only for monitoring the unit, and not during the
real-time simulation.
1 Restrictions to using MUSE with OPAL-RT Board software architecture may apply depending on your application and software configuration. Please contact
your sales representative or field application engineer to verify compatibility
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