Panasonic DMR-ES10P

17.4. Analog Timer Block Diagram
H
H
H
L
L
H
H
H
L
H
L
H
H
IC7503
(SYS PFAIL OUT)
QR7503
D+3.3V21
(SYS PFAIL CTL.)
VDDOUT
Q7508
Q7507
CONTROL
P SAVE
78P SAVE
3
SYS PFAIL 81
POWER
S7001
P7505
3
P7001
DMR-ES10P/PC
Analog Timer Block Diagram
BLOCK SECTION
TO AUDIO
(RESET)
IC7502
X SW+5.2V
12 VDD OUT P FAIL
80
QR750279FILAMENT ON
JC P ON
CV IN
L123 SWIDE
SYNC IN
21
F+
F-
1
8
5
9
47
1
T7501
REGULATOR
DISPLAY
IP7501
PROTECTOR
IC
Q7506
CONTROL
FIP
XSW+5.2V
49
- -
SEG35
SEG39
45
17SEG26
-
SEG00
-
19
44
SEG25
56
63
-
DIG07
-
DIG00
SDATA
SCK
CS
RESET1
2
3
4
VP
64
IC7501
(DISPLAY DRIVE)
FL RXD 5
48 P SAVE
XC OUT
XC IN
10
9
(REAL TIME CLK)
32.768KHz
X7501
113
PLAY
S7502
S7506
CH-UP
IC7505
(TIMER)
FRONT(L)P.C.B.
X SW+5.2V
IR7501
132
L1 SWIDE
SYNC IN
XT MUTE
X OUT
X IN
DR P ON
DI P ON
P SAVE
FL TXD
FL CLK
FL CS
FL RESET
KEY IN1
REMOCON
KEY IN2
KEY IN3
99
109
63
12
14
50
49
51
4
6
94
93
101
2
102
104
DP7501
DISPLAY
TIMER
(MAIN CLK)
10MHz
X7502
X SW+12V
POWER ON
DR P ON
JC P ON
BLOCK SECTION
FROM VIDEO
XT MUTE
BLOCK SECTION
POWER
TO
SEG00-SEG39
DIG00-DIG07
S7505
CLOSE
OPEN/
SENSOR
REMOTE CTL.
REC
S7501
S7507
CH-DOWN
STOP
S7503
IC7506
XSW+5.2V54
(X RESET)
VDDOUTXRESET 11
DMR-ES10P / DMR-ES10PC
39