Command Reference 8-111
:STATus :QUEStionable :ENABle
8 <Decimal data>
Enable Questionable Data/Signal Status Reporting
Sets the enable bits of the status questionable enable register. This enable register
contains a mask value for the bits to be enabled in the status questionable event
register. A bit that is set true in the enable register enables the corresponding bit in
the status register. See figure on page 8-110.
An enabled bit will set bit #3, QUE (Questionable Status Bit), in the Status Byte
Register if the enabled event occurs. See also status reporting on page 3-10.
Power-on will clear this register if power-on clearing is enabled via *PSC.
Parameters:
<dec.data> = the sum (between 0 and 17920) of all bits that are true. See the table on page
8-110.
Returned Format: <Decimal data> ¿
Example:
Send ®
:STAT:QUES:ENAB 8 16896
In this example, both ‘unexpected parameter’ bit 14, and ‘overflow’ bit 8, will set the
QUE-bit of the Status Byte when a questionable status occurs.
Complies with standards: SCPI 1991.0, confirmed.
:STATus :QUEStionable?
Read Questionable Data/Signal Event Register
Reads out the contents of the status questionable event register. Reading the
Status Questionable Event Register clears the register. See figure on page 8-110.
Returned Format:
<dec.data> = the sum (between 0 and 17920) of all bits that are true. See the table on page
8-110.
Complies with standards: SCPI 1991.0, confirmed.
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