VBUS
D-
D+
YEL
YEL
GRN
GRN
TPO+
TPO+
TPO-
TPO-
TPI+
TPI+
TPI-
TPI-
Page: 01 of 01
Time:02:46:06 PM Date:03/01/2006
DWG
NO.
1234
Pitney Bowes
WORKMANSHIP PER PB PROCEDURE B1850
UNLESS OTHERWISE SPECIFIED:
TOLERANCES
0.03
0.01
0.005
ONE PLACE DECIMALS
TWO PLACE DECIMALS
THREE PLACE DECIMALS
+
-
-
-
+
+
CLASSIFICATION OF CHARACTERIS
PER PB B1525
CRITICAL
MAJOR
MINOR
ALL OTHER CHARACTER
D
S
DO NOT SCALE THIS DRAWING
PROJECTION
THIRD ANGLE
REQNEXT ASSEMBLY
PRODUCT
CODE
CHANGE ORDER NO
SCALE
DATE
PART NO
MODEL
TITLE
APPROVED
DRAWN
DATE
N
1
261-2732
J4
2
3
4
5
6
7
8
9
10
1
J1
261-3252
2
3
4
5
6
MTG-HOLE
MH1
MTG-HOLE
MH2
100pF
C3
100pF
C4
6.8V 5W
D1
CONN_F
J2
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
261-3449
1
4
2
3
5
6
7
8
9
10
11
12
13
14
15
16
YEL
GRN
4.7uF
C2
0.1uF
C1
4
261-3017
1
J3
2
3
4
5
6
J5
1
2
3
WS92009
2/24/06
2/24/06
CO10343
YOUNG LEE
JOG
WSX
NOTES:
1. UNLESS OTHERWISE SPECIFIED:
ALL RESISTORS ARE IN OHMS, +/-5%
AND 1/10 WATT. ALL CAPACITANCE
VALUES ARE IN MICROFARADS (uF).
2. FOR ASSEMBLY DRAWING SEE WS82009.
REF
CCWS82009WSXX
LAYOUT NOTES:
1) BOARD IS TWO LAYER
2) ALL TRACES SHOULD BE ON TOP SIDE
IF POSSIBLE
3) TOP IS COPPER POUR 3.3V
4) BOTTOM IS COPPER POUR GND
5) C1 AND C2 ARE LOCATED AS CLOSE TO
J5 PIN1 AS POSSIBLE
6) C3 AND C4 ARE LOCATED AS CLOSE AS
POSSIBLE TO THEIR RESPECTIVE
MOUNTING HOLES
7) LOCATE D1 NEAREST AND BETWEEN J1
AND J2
8) J1 AND J2 ARE ON BACKSIDE
9) J4 AND J5 MUST HAVE THEIR LATCHES
FACING AWAY FROM EACH OTHER.
10) REFER TO MECHANICAL DESIGN FOR
CRITICAL PLACEMENT OF PARTS
WS9200
BOARD
PASS THROUGH
CONNECTION
PANEL
CONNECTION
PANEL
CONNECTION
BOARD
PASS THROUGH
CONNECTION
SCH - USB/LAN INPUT BD
ETHERNET LAN
USB FUNCTION
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