5 ASIC Interface
Mode Register 0, Low-Byte, Address 06H (Intel):
bit 7
Freeze_Supported: Freeze_Mode support
0 = Freeze_Mode is not supported.
1 = Freeze_Mode is supported
bit 6
Sync_Supported: Sync_Mode support
0 = Sync_Mode is not supported.
1 = Sync_Mode is supported.
bit 5
Early_Rdy: Early Ready
0 = Normal Ready: Ready is generated when data is valid (write) or when data
has been accepted (read).
1 = Ready is generated one clock pulse earlier
bit 4
INT_Pol: Interrupt Polarity
0 = The interrupt output is low-active.
1 = The interrupt output is high-active.
bit 3
minT
SDR
: Default setting for the minT
SDR
after reset for DP operation or
combi operation.
0 = Pure DP operation (default configuration!)
1 = Combi operation
bit 2
WD_Base: Watchdog Time Base
0 = Watchdog time base is 10 ms (default state)
1 = Watchdog time base is 1 ms
bit 1
Dis_Stop_Control: Disable Stopbit Control
0 = Stop bit monitoring is enabled.
1 = Stop bit monitoring is switched off
Set_Prm telegram overwrites this memory cell in the DP_Mode. (Refer to the
user specific data.)
bit 0
Dis_Start_Control: Disable Startbit Control
0 = Monitoring the following start bit is enabled.
1 = Monitoring the following start bit is switched off
Set_Prm telegram overwrites this memory cell in the DP_Mode. (Refer to the
user specific data.)
Figure 5-1: Coding of Mode Register 0, Low-Byte
20 Revision 1.03
VPC3+C
User Manual
Copyright © profichip GmbH 2004-2006
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