Profichip VPC3+C - 10.7.3 Timing in the Asynchronous Intel Mode

Operational Specifications 10
10.7.3 Timing in the Asynchronous Intel Mode
In the asynchronous Intel mode, the VPC3+C acts like a memory with
ready logic. The access time depends on the type of access. The request
for an access to the VPC3+C is generated from the falling edge of the read
signal (XRD) or the rising edge of the write signal (XWR).
The VPC3+C generates the Ready signal synchronously to the system
clock. The Ready signal gets inactive when the read or the write signal is
deactivated. The data bus is switched to Tristate with XRD = '1'.
AB10..0
DB7..0
XRD
valid
data valid
XCS
X
READY
(normal)
X
READY
(early)
22
27
26
25
24
23
17
16
18
19
20
21
Intel Mode, READ (XWR = 1) Figure 10-12: Asynchronous
VPC3+C User Manual
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