Profichip VPC3+C - Page 88

10 Operational Specifications
AB10..0
valid
DB7..0
XWR
XCS
data valid
X
READY
(normal)
X
READY
(early)
22
27
25
30
23
28
16
29
19
26
20
21
Figure 10-13: Asynchronous Intel Mode, WRITE (XRD = 1)
VDD = 3.3 V VDD = 5 V
No. Parameter
MIN MAX MIN MAX
Unit
16
address-setuptime to XRD / XWR ↓
0
0 ns
17
XRD ↓ to data valid
103
97 ns
18 XRD pulsewidth 115 115 ns
19
XCS ↓ setup
0 ns
time to XRD / XWR ↓
0
20
XRD ↓ to XREADY ↓ (Normal-Ready)
132
126 ns
21
XRD ↓ to XREADY ↓ (Early-Ready)
111
105 ns
22 XRD / XWR cycletime 125 125 ns
23
address holdtime after XRD / XWR ↑
0
0 ns
24
data holdtime after XRD ↑
4 16
4 13 ns
25 read/write inactive time 10 10 ns
26
XCS holdtime after XRD / XWR ↑
0
0 ns
27 XREADY holdtime after XRD / XWR 6 21 5 16 ns
28
data setuptime to XWR ↑
10
10 ns
29 XWR pulsewidth 83 83 ns
30
data holdtime after XWR ↑
10
10 ns
Figure 10-14: Timing, Asynchronous Intel Mode
88 Revision 1.03
VPC3+C
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