8 Hardware Interface
used in the synchronous Intel mode. One figure shows the minimum con-
figuration of a system with the VPC3+C, where the chip is connected to an
EPROM version of the controller. Only a clock generator is necessary as an
additional device in this configuration. If a controller is to be used without an
integrated program memory, the addresses must be latched for the external
memory.
Notes:
If the VPC3+C is connected to an 80286 or similar processor, it must be
taken into consideration that the processor carries out word accesses. That
is, either a ‘swapper’ is necessary that switches the characters out of the
VPC3+C at the correct byte position of the 16-bit data bus during reading or
the least significant address bit is not connected and the 80286 must read
word accesses and evaluate only the lower byte.
Name
Input/
Output
Type Comments
DB(7..0) I/O Tristate High-resistance during RESET
AB(10..0) I AB(10) has a pull down resistor.
MODE I Configuration: syn/async interface
XWR/E_CLOCK
AB11
I
Intel: Write Sync. Motorola: E-Clk
AB11 (Asynchronous Motorola Mode)
XRD/R_W I Intel: Read Motorola: Read/Write
XCS
AB11
I
Chip Select
AB11 (Synchronous Intel Mode)
ALE/AS
AB11
I Intel/Motorola: Address Latch Enable
AB11 (Async. Intel / Sync. Motorola Mode)
DIVIDER I Scaling factor 2/4 for CLKOUT 2/4
X/INT O Push/Pull Polarity programmable
XRDY/XDTACK O Push/Pull * Intel/Motorola: Ready-Signal
CLK I 48 MHz
XINT/MOT I Setting: Intel/Motorola
CLKOUT2/4 O Push/Pull 24/12 MHz
RESET I Schmitt-Trigger Minimum of 4 clock cycles
Figure 8-2: Microprocessor Bus Signals
* Due to compatibility reasons to existing competitive chips the XRDY/XDTACK output of the
VPC3+C has push/pull characteristic (no tristate!).
70 Revision 1.03
VPC3+C
User Manual
Copyright © profichip GmbH 2004-2006
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