Section 3
Principles of Operation
3.2.4
Interface Control
The Small Computer System Interface (SCSI) logic is implemented using an SCSI controller chip called
SPICY. This chip interfaces to the host system through the 50-pin SCSI connector (11); and to drive
electronics including the microprocessor's control lines and address/data bus, and the DMA controller/data
sequencer
(SOLO).
The controller chip is configured to operate under control
of
the microprocessor, which can send and receive
information through the multiplexed address/data bus. An address is strobed into the
SCSI controller chip
on
the falling edge
of
ALE (Address Latch Enable). Data is then strobed from or onto the bus by -RD (read
status from the controller chip)
or
-WR (write to
the~ontroller
chip)
if
the address selects the chip.
The microprocessor can also command
SPICY to perform data transfer operations between the SCSI bus
and the buffer RAM in synchronous or asynchronous mode.
SPICY reads
or
writes data from/to the buffer
RAM over nine lines (eight data lines and one parity line). The transfer is controlled by the DMA
controller/data sequencer IC
(SOLO) which handles addressing
of
the buffer RAM for SPICY. Data can be
transferred between the buffer RAM and
SPICY at up to 8.0 MBytes/second in SOLO page mode
operations. This high
DMA
transfer rate allows SPICY to communicate over the SCSI bus at a
synchronous data rate
of
4.0 MBytes/second, while SOLO simultaneously controls disk-to-RAM transfers
and RAM refresh operations.
3 - 6 Principles
of
Operation
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