RCA 70/46 - Page 131

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Set

Program

Mask

(SPM)

General Description

Format

(RR)

Condition Code

Program

Mask

Processor

State Control

Instructions

• Bits 2-7

of

the general

register

specified by

the

first address

(R

1

)

establish new

program

masks

and

condition code

setting

for

the

current

program

state.

04

o

7 8

11 12

15

• The condition code is

set

according to

bits

2

and

3

of

the

general

register

specified

by

Rl

as

follows:

Condition Code Setting

2

3

Result

0 0

Set

condition code 0

(zero).

0 1

Set

condition code 1.

1 0

Set

condition code

2.

1 1

Set

condition code 3.

• The

program

mask is

set

according to

bits

4-7

of

the

general

register

specified

by

Rl

as

follows:

Program

Mask

Setting

Bit

Result

4

Fixed-point

overflow.

5

Decimal overflow.

6

Exponent

underflow.

7

Significance

error.

Note • The contents

of

the

P-counter

and

the

register

specified by

the

first

address

are

unaltered.

122

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