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Supervisor Call
(SVC)
General Description
Format
(RR)
Condition Code
Interrupt Action
Note
Processor
State Control
Instructions
• The R1 and R2 fields provide an interruption code and this code is placed
into
the rightmost byte of the Interrupt Status Register (ISR) of the
program state in which this instruction is issued. The supervisor call
interrupt flag bit (priority 21) is set in the Interrupt Flag register and a
program interrupt may occur depending on the associated mask bit in the
Interrupt Mask register of the current state.
o 7 8 11 12 15
• Unchanged.
•
None.
• If a higher priority interrupt is honored upon executing this instruc-
tion, the flag bit (priority 21) will be set and the Supervisor Call byte
stored
in the ISR so that when it is honored, the results are independent
of any higher priority interrupts.
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