Renesas TPS-1 User Manual

TPS-1 User’s Manual: Hardware 2. Pin function
R19UH0081ED0107 Rev. 1.07 page 12 of 86
Jul 30, 2018
L11 SCLK_2_INOUT O Fiber Optic Port 2: I
2
C-Bus “Clock” e.g. SC-RJ
C11
LINK_PHY2
O
LINK indication ETHERNET Port 2 (up or down)
(active high)
A10 ACT_PHY2 O Activity ETHERNET Port 2 (active high)
J13
P2_TX_P
O
ETHERNET Port 2 Transmit Data (positive)
e.g. RJ45
J14 P2_TX_N O ETHERNET Port 2 Transmit Data (negative) e.g. RJ45
K13 P2_RX_P I ETHERNET Port 2 Receive Data (positive) e.g. RJ45
K14
P2_RX_N
I
ETHERNET Port 2 Receive Data (negative)
e.g. RJ45
N8
P2_SD_P
I
Fiber Optic Port 2: Signal Detect (positive)
e.g. SC-RJ
P8 P2_SD_N I Fiber Optic Port 2: Signal Detect (negative) e.g. SC-RJ
N9
P2_RD_P
I
Fiber Optic Port 2: Receive Data (positive)
e.g. SC-RJ
P9 P2_RD_N I Fiber Optic Port 2: Receive Data (negative) e.g. SC-RJ
N6 P2_TD_OUT_P O Fiber Optic Port 2: Transmit Data (negative) e.g. SC-RJ
P6
P2_TD_OUT_N
O
Fiber Optic Port 2: Transmit Data (positive)
e.g. SC-RJ
P5
P2_FX_EN_OUT
O
Fiber Optic Port 2: Transmitter enable (active high)
e.g. SC-RJ
Oscillator
N11
XCLK1
I
Connection external oscillator (1), 25 MHz
P11 XCLK2 O Connection external oscillator (2), 25 MHz
JTAG – Interface
L4 TM0 I Test Input 0 (Chip Test - 10k to GND) (pull down external)
J10
TM1
I
Test Input 1 (Chip Test - 10k to GND)
(pull down external)
K5 TRSTN I JTAG-Interface: “Test Reset” (pull down external)
L6
TMS
I
JTAG-Interface: “Test Mode Select”
(pull-up external)
L7 TDO O JTAG-Interface: “Test Data Output”
J5 TCK I JTAG-Interface: “Test Clock” (pull-up external)
L5
TDI
I
JTAG-Interface: “Test Data Input”
(pull-up external)
Reset / Test
A12 RESETN I TPS-1 Reset (Global Reset) (active low)
H12
ATP
I
Test pin for production test (n.c.)
H13 EXTRES O External reference resistor (12.4 kΩ,1 %), connect to
analog GND
E10
TMC1
I
Test Mode Control 1 (production test)
(pull down external
recommended)
K10 TMC2 I Test Mode Control 2 (production test) (pull down external
recommended)
D6
TEST_1_IN
I
Test Pin 1 for hardware test of the TPS-1
(pull down external
recommended)
D7 TEST_2_IN I Test Pin 2 for hardware test of the TPS-1 (pull down external
recommended)
D8
TESTDOUT5
O
Test Data Output 5 (High Speed Signals for PHY)
D9
TESTDOUT6
O
Test Data Output 6 (High Speed Signals for PHY)
L8
TESTDOUT7
O
Test Data Output 7 (High Speed Signals for PHY)
Host interface
A11
WD_IN
I
Watchdog input (from the Host) (the rising edge resets
the watchdog counter of the TPS-1)
(active high)
B12 WD_OUT O Watchdog output (to the Host) (active low)
K11
INT_OUT
O
Interrupt output (to the Host)
(active high)
Boot interface (serial)

Renesas TPS-1 Specifications

General

Brand	Renesas
Model	TPS-1
Category	Controller
Language	English