Rigol DS8000-R Series User Manual

RIGOL Chapter 11 Protocol Decoding
11-16 DS8000-R User Guide
related to the value of the horizontal time base) is dispalyed.
SPI Decoding (Option)
SPI bus is based on the master-slave configuration and usually consists of chip select
line (CS), clock line (CLK), and data line (SDA). Wherein, the data lines include the
master input/slave output (MISO) data line and master output/slave input (MOSI)
data line. The oscilloscope samples the channel data on the rising or falling edge of
the clock signal. The oscilloscope will also judge each data point (logic "1" or logic "0")
according to the preset threshold level.
Master
Slave
MOSI
CLK
MISO
CS
CLK
SDA
(MISO/MOSI)
Figure 11-7 SPI Serial Bus
In the decode setting menu, click Decode1 → Bus Type to select "SPI".
1． Enable or disable the bus
Click Bus Status to enable or disable the decoding function.
The detected ACK is 1

Rigol DS8000-R Series Specifications

General

Brand	Rigol
Model	DS8000-R Series
Category	Test Equipment
Language	English