Sanwa PC20TK - Page 21

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Fig. 3-14: Diagram showing the operation of double integration
Fig. 3-15: Timing chart for double integration
Input
voltage
Vi
Reference
voltage Vref
Point A
Input selection
switch
Controls turning
ON/OFF SW1 and
SW2
Reset signal
t2 detection signal
Latch signal
Latch/decoder
Count signal
t3 detection signal
Reset
signal
Switch selection signal
Gate opening signal
Clock pulse
Control circuit
Double integration type A/D converter Readout
Counter
Gate
Integration circuit
Comparator
Output voltage
Vo of integration
circuit
0-voltage detection signal is generated
Latch signal is generated
Reset signal is generated
(Controller)
Input voltage
Input voltage
of integration
circuit
Output voltage
of integration
circuit
Reverse integration period
Integration
period
Output voltage
of comparator
Clock pulse
Gate opening
time
When input
voltage is V
When input
voltage is V'
Number of
pulses that pass
through the gate