Sequential prophet 5 - Page 31

Computer output consists of CV and switch (S) signals. All circuits which extract data from the micro¬
computer system are based on the latch. The latch is a one-address digital memory, used to hold data
for an output circuit during the period when the CPU is busy with other operations. Latched data is
"refreshed" every loop. For example, a single latch may capture ON/OFF commands for six switches.
The switch commands remain valid until the CPU next sends data to the latch.
The DAC's basic function has already been introduced — it converts computer data to an analog
voltage. But the synth requires 41 CVs. Forty-one DACs. each connected to a CV desination. could be
used. More efficiently, the Prophet uses one OAC and a CV demultiplexer (CV DMUX) to distribute
the DAC output. VDAC. VDAC assumes the value of all 41 CVs during each program loop. (See Figure
2-2. below). Since CV distribution is sequential, an analog equivalent to the latch is also required.
Forty-one sample-and-holds perform this function. Each S/H maintains a specific VDAC value during
the period when the CPU is otherwise occupied. The CV output remains constant until the S/H is
strobed (refreshed) during the next loop.
To exemplify the process, suppose the FIlT ATK CV is to be set to 7.083V. In MANUAL mode this value
would originate directly from the control knob. In PRESET, this value would be read from the
NV PRCM RAM. In either case, the CPU places the binary number 1010101 on to the DATA BUS. and
the OUT PORT DCOD issues CSC. This causes the DAC LATCH Q outputs to follow the state of the
DATA BUS — until the next appearance of CSC.
The latched bits drive a level amplifier consisting of transistors operated from a voltage reference.
This stage insures that the normally uncritical digital signals are equal and constant. Thus; the level
amp output is “precisely" low or high, following the latched bits. The R-2R ladder binary-weights the
current through each ladder "rung", so VDAC. through U328. assumes the value shown. In the
example, the bit patern 1010101 converts to a VDAC of 7.083V. The current addition performed by the
ladder is shown.
The exact DAC scaling is 1/12V (83.3 mV) per step. This was chosen for convenience in controlling the
OSC and FILT FREQs, which are scaled at IV/octave. With these values, each step results in a fre¬
quency change of exactly one semitone. (Which is why the OSC FREQ knobs adjust in semitones.)
The 7-bit DAC has a range of 128 steps, thus 0 - 10.583V (127 X 1/12V). In actual practice the DAC MSB
is not used for frequency control since only about half the full range is needed to represent either the
five-octave (61 note) range of the keyboard or the OSC (INIT) FREQ knobs.
Returning to the example, the CV DMUX can be thought of as a single pole. 41 position rotary switch
in which the switch position (address) is controlled by data from another set of latches. The address
currently routes VDAC to the first DMUX output, to which is connected the sample and hold (S/H).
The S/H is a short-term analog memory comprised of a low-leakage capacitor and a )-FET-input
operational amplifier, nicknamed a BIFET. The BIFET has an extremely high input impedence —
several thousand megohms — and is configured for unity gain. With VDAC applied, the FILT ATK CV
ideally equals 7.083V.
To output the next CV, first the CV DMUX address changes, the new data is latched to the DAC. In the
meantime Cl holds its charge, since there is no leakage path. The S/H output voltage thus remains
constant. CVs value is large enough to hold the charge for at least 10 ms (the CPU "scan" rate), but low
enough so it quickly recharges to a higher or lower VDAC when it is next strobed. The process con¬
tinues for the remainder of the S/Hs. In summary, though the CPU generates CVs sequentially, the
S/Hs make sure that the analog circuitry never knows the difference.
To generate switch commands, a latch alone is used. The Q outputs connect to the Scontrol lines. The
latched data 101010 would therefore close (11 three corresponding switches and leave three open |0).
Unlike the DAC. the switches don't care about the actual numerical value of the data, since each
switch is only connected to one bn. In other words, the same data which represent a CV value of
3.500V (101010 x 1/12V) 10 the DAC. stands for a combination of Of F/ON < ommands when latched
instead to switches.
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