Sequential prophet 5 - Sd212 Control Panel-Switch and Led Matrices; Sd311 Computer-Cpu. Memory. I;O

ponding inputs on each <051. When high, the I inputs INHIBIT the 4501. So to select just one pot one,
and only one, of these bits must be 0.
U210's state is undetermined on power-up. since the computer has not yet had time to initialize the
POT MUX. U210 might well “come up" with more than one 0 for Q4, Q5. or Q6. In such cases,
two or more pots would be connected together (at VMUX). The current surge resulting from any
significant potential difference between the pots would instantly destroy the 4051s, were it not not
for R214/15/16.
2-19 SD212 CONTROL PANEL — SWITCH AND LED MATRICES
The SWITCH and LED MATRICES are also divided across PCBs 1 and 2. The keyboard connects to
PCB2 to share bus driver packages with the switches. The LED matrix indudes the elements of DS225
BANK/PROGRAM display, all 7-segment decoding done by software.
The program scans the keyboard first. Scanning places a bit across one coordinate of the switch
matrix, then checks the intercepting coordinates for its appearance. The resulting number uniquely
identifies a combination of switch closures. For example, the CPU sends 00000001 (1H) to U209/12
switch driver latches, with CS8 from the OUT PORT DCOD. DX0 is now 1. DX1-7 are 0. This "sets up"
the lowest eight keys. Each key is located on a binary column, and closing its switch adds the corre¬
sponding bit weight to the number driven on to the bus (read) by -CSE from the IN PORT DCOD.
Suppose DO is held. DY2 would be 1, resulting in 00000100 (4H). If GO were also held. 10000100 (132H)
would be read.
To scan the next eight keys, DX1 is set and the DY columns again read. The process continues for
DX2-DX7. Note that three control switches are wired in the keyboard matrix. This is no problem. The
computer “knows" that any number read from DX7 larger than 31H, must include one of these switch
operations.
The control switches are read in similar fashion, with -CSE from the IN PORT DCOD, except SI 12 EDIT
and S113 TUNE each drive two columns. Separately clocked sections of the U204/5 BUS DRIVERS are
paralleled for hardware efficiency. The driver OUTs are tri-stated (high impedence) except when
their corresponding DIS pins go low.
In the LED matrix, U213/14/15 current sinks invert DX0-DX5 to effectively ground the paths
through Q201-Q208. Latched bits are inverted at the -Q outputs of U208/11. then again by the
transistor switches. To light DS205 and DS204. for example, first CS8 would latch 1H. then CS9
(also from OUT PORT DCOD) would latch 3H. To operate DS225. bits latched by CS9 correspond
to the display segments required. For example, to display BANK 2, CSfl latches 10H (DX4 B 1),
then CS9 latches 5BH (01011011) to light segments a. b. d. e, and g. (The LEDs must be cleared
to read the switches.)
2-20 SD311 COMPUTER — CPU, MEMORY, I/O
Almost the reason for the computer itself. U301-308 NV PRGM RAM may represent a large invest¬
ment of the musician's time. Many steps have been taken to protea it.
With power OFF, BT301 holds RAM data by providing 2.3 Vdd through D304. Current drain is less
than 10 tiA, giving the battery a life-expeaancy of ten years.
For use when probing the computer, S301 prevents the CPU from writing into NV by disabling -WR
from U311-22. When OFF. S301 also disables the TUNE routine, since BIAS values too are stored in
the NV RAM. (Be sure to switch S301 back ON when done.)
Normally S703 (see SD711) prevents accidental recording into NV, by grounding the active high
MEM EN signal. It is read with -CS10 at U329 (SD312).
2-22