Sequential prophet 5 - Sd312 Adc. Dac, Common Analog

CLK 1 increments Counter 1 at the CPU clock rate.
Since Counter 0 has been programmed to count 1 cycle, the next rising edge on U316-9 causes OUT 0
to go HI, stopping Counter 1, and signalling the CPU that counting has concluded. The CPU fetches
Counter 1's 16-bit contents (in two 8-bit pieces) and saves this first count for reference. The periods
of the remaining oscillators are measured similarly. To count each oscillator at 600,1200, and 2400 Hz,
Counter 0 is loaded with 2, 4, and 8, respectively.
2-21 SD313 ADC, DAC, COMMON ANALOG
The ADC is based on a DATEL MC8BC. It contains a binary counter and internal DAC. The counter
increments until the DAC output compares to the analog voltage being measured. The comparison
stops the counter and notifies the CPU to fetch the counter value through the bus drivers.
In more detail, to convert a POT value the CPU issues ST CONV to U321-4. U321-6 goes low, reset¬
ting U334's internal counter and setting status latch U333-1. U333-3 goes high, enabling U333-6
GATED CLOCK. The GATED CLOCK strobes U334-4 at about 500 kHz. incrementing the binary
counter. U334-14 ANA OUT is a ramp which lengthens with higher pot settings. See Waveforms 2-0
and 2-1. When it compares with buffered (U338) and scaled (R302) VMUX. the resulting pulse resets
the latch. U333-3 goes low, interrupting the CPU which then fetches the counter value with -CSF,
starts the next conversion, and returns to what it was doing.
Potentiometer drift is eliminated through software “hysteresis'' which watches the direction of value
changes. A pot must move two bits in the same direction to qualify as a legitimate change.
R101
FILT
CTF
U334-14
V: 200 mV/div
H: 2 ms/div
Waveform 2-0
ADC ANALOG OUTPUT
2-24