Sequential prophet 5 - Page 40

Norhing can proiect the NV PRGM RAM from memory loss if the technician shorts Vdd to ground,
or disconnects It. However, the POWER DETECTION circuit can prevent power source •'dropouts
as short as 10 ms from interfering with RAM write operations. The NV RAM is vulnerable 10 these
fluctuations because with power falling. U312/13 EPROMs may cause erroneous data to be written
into NV if the CPU is still being clocked. At power-off ♦ V through J710/P301-10 drops out first,
R3177/178 divides *V down to the CMOS logic threshold of 3.5V. Thus. U309-10 immediately goes
high, disabling the clock at U322-6.
U309 is also powered bv BT301. With power off U309-10 is high: so are U309-6 and. through D307.
U309-5. UJ09-4 is low. holding U311-26. the CPU RESET. When power h switched on. *V will take the
longest time to reach its lull value. Thus after all the other voltages have developed. U309-10 goes
low. This enables the clock (U322-6). holds U309-6 low and begins to pull down U309-5 through
RJ176. The time constant of C390 and R 1176 is such that U309-4 goes high, starting U311. about 1 sec
after the clock starts.
As a final measure the NV PRGM RAM -CS. which must be low to write, is not allowed to go low
when power is going up or down. -CS and -WR arc gated through U309-13 so U309-1 goes low only
when U309-10 also delects full power. The 74C02 was chosen for lower propagation delay than
the 4001. allowing the CPU to access NV PRGM RAM without having to enter WAIT states.
U319 MEM ADR DCOD selects each memory device by a gated -MREQ and the most significant
address lines (see TABLE 2-1). -RD and -WR are also gated to the two RAMs. -WR clocks the memory’s
internal latches. -RD clocks their bus drivers, for example, the -CS from U319 -10 and -RD. enable
U317/18's "A” sections.
I/O devices are selected by CSs from U323/25/26 IN and OUT PORT DCODs. U323 ANDs -RD with
A0-A2. U324 ANDs -WR with A3-A5. U32S shifts logic levels to clock high-voltage (CMOS) latches
U357/63/56/61/62/60. U355 similarly shifts DATA BUS levels for these latches. High-voltage latches
are required to control analog switches which must pass 10-V level waveforms. Current-limiting
resistors such as R3140/41/42 are installed wherever the bit controls a type 13202 switch. 13202s are
used wherever a bipolar (triangle) waveform may be passed. U357 (CS6) latches the five gates. U356
(CS4) andU363 (CSS) latch CV DMUX and TUNE MUX addresses.
The SEQ GATE BFR consists of a level-shifting circuit (U322-10/11) an OR-gate and inverter. A switch
on 1703 SEQ GATE IN (see SD711) is read with -CSIOat U330 (see SD312). If -SEQ GATE EN is low. GATE 5
(U357-12) is switched off by the CPU. and the external device gates VOICE 5.
Addressed as a memory device. TIMER U316 contains three programmable counters. Counter 2
divides the CPU clock frequency by a large integer to provide a 440-Hz reference. It is enabled by a bit
latched by U331. Counters 0 and 1 comprise the TUNE circuit, as follows.
As outlined in paragraph 2-15 the CPU first selects OSC 1A by latching the appropriate addresses with
U356 (S/H A.B.C) and U363 (S/H 18). U416 LEVEL COMPARATOR (SD313) converts oscillator sawtooth
to pulses which are negative in proportion to the sawtooth period. TUN EN from U331-10 then starts
Counter 0. which is clocked by -TUN MUX. CLK 0 first initializes Counter 0 to 1 (cycle), from a pre¬
viously loaded internal register. OUT 0 goes low on the next falling edge of CLK 0. and gates Counter 1
through inverter U321-8. TUN STATUS is 0. signifying to the CPU when latched at U317-14. that the
TIMER is counting.
TABLE 2-1
MEMORY ADDRESSES
0000
-03FF EPROM 0
U312
IK BYTES
0400
-07FF EPROM 1 U313
IK BYTES
0800
-0BFF EPROM 2 (NOT USFDt U314
ocoo
-0C0) TIMER U316
4 BYTES
1000
-107F SCRATCHPAD RAM
U315
128 BYTES
1400
-17FF
NV RAM
U301-U308 IK BYTES
2-23