Programming made easy
6.6 High-speed counter (HSC)
Easy Book
120 Manual, 03/2014, A5E02486774-AF
HSC input channel selection
Use the following table and ensure that the CPU and SB input channels that you connect
can support the maximum pulse rates in your process signals.
Note
CPU and SB input channels (V4 or later firmware) have configurable input filter times
Earlier firmware versions had fixed HSC input channels and fixed filter times that could not
be changed.
V4 or later versions allow you to assign input channels and filter times. The default input filter
setting of 6.4 ms may b
e too slow for your process signals. The filter times for the HSC
inputs must be optimized for your HSC application.
See "Configuring digital input filter times"
Table 6- 28 CPU input: maximum frequency
A/B Quadrature phase
mode
1212C
1214C and 1215C
1217C
Ib.2 to Ib.5
(.2+, .2- to .5+, .5-)
1 MHz 1 MHz
Table 6- 29 SB signal board input: maximum frequency (optional board)
A/B Quadrature phase
mode