Sony HBD-DZ950 - Page 38

DAV-DZ350/DZ650/DZ950
38
IC501 – 503 TAS5352A
23
25
34
35
GVDD_D
24
BST_D
NC
26
PVDD_D
27
PVDD_D
28
OUT_D
29
GND_D
30
GND_C
31
OUT_C
32
PVDD_C
33
BST_C
BST_B
PVDD_B
36
OUT_B
37
GND_B
19
20
7
6
5
4
3
2
1
NC
NC
21
VDD
22
GVDD_C
RESET_AB
8
PWM_B
9
OC_ADJ
10
GND
11
AGND
12
VREG
13
M3
14
M2
15
M1
16
PWM_C
18
PWM_D
17
RESET_CD
PWM_A
SD
NC
NC
OTW
GVDD_B
PWM
RECEIVER
GATE
DRIVE
PROTECTION
AND
I/O LOGIC
CONTROL TIMING
I SENSE
PWM
RECEIVER
GATE
DRIVE
CONTROL TIMING
PWM
RECEIVER
GATE
DRIVE
CONTROL TIMING
PWM
RECEIVER
GATE
DRIVE
CONTROL TIMING
INTERNAL PULL UP
RESISTORS
TO VREG
VREG
3
UNDER-VOLTAGE
PROTECTION
POWER ON
RESET
TEMPERATURE
SENSE
OVERLOAD
PROTECTION
BTL/PBTL
CONFIGURATION
PULL DOWN RESISTOR
BTL/PBTL
CONFIGURATION
PULL DOWN RESISTOR
BTL/PBTL
CONFIGURATION
PULL DOWN RESISTOR
38
39
GND_A
OUT_A
40
PVDD_A
41
PVDD_A
42
NC
43
BST_A
44
GVDD_A
BTL/PBTL
CONFIGURATION
PULL DOWN RESISTOR
4
4