Sony PMC-DR45L - IC Block Diagrams

– 67 – – 68 –
24 23 22 21 20 19 18
1 2 3 4 5 6 7
17 1516 1314
111098 12
OSC
OUT
AM
OSC IN
AM
RF IN
AM
AGC
AM
DET OUT
FM
DET OUT
PLL
IN
MPX
IN
PILOT
DEL
R
OUT
L
OUT
AFC
AM
IF IN
REGAM
MIX OUT
FM
IF IN
GND TU
LED
ST LED FM DET VCC IF OUT BAND
S/W
ST
S/W
ALC
AGC
COMP
REG
S-CURVE
AM
OSC
FM
IF
FM
DET
AM
MIX
AM
IF
AM/FM
IF
BUFF
AM
DET
DECODER
ANTI-BIRDIE
PILOT
CANCEL
STEREO
SW
P-DET
Ø
VCO
304kHz
AM
RF. AMP
BUFF
LEVEL
DET
TUNING
DRIVE
GND VCC
FF
38k
FF
19k/0
PILOT
DET
FF
19k/2
π
12
11
10
9
8
7
6
5
4
3
2
1
13
14
15
16
17
20
21
UNLOCK
DETECTOR
POWER ON
RESET
UNIVERSAL
COUNTER
CCB
I/F
NC
CE
DI
CL
DO
XOUT
22
NC
AOUT
XIN
AIN
PD
VSS
VDD
B04
FMIN
AMIN
B01
B02
B03
I01
I02
IFIN
PHASE
DETECTOR
CHARGE
PUMP
REFERENCE
DIVIDER
SWALLOW
COUNTER
1/16,1/17
4BITS
12BITS
PROGRAMMABLE
DIVIDER
DATA SHIFT REGISTER
LATCH
1/2
18
19
1
2
3
4
8
9
10
11
12
7
18
19
20
21
22
23
24
17
16
15
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
6
VEE
VEE
VC
VEE
VCC
VCC
VREF
APC PD AMP
APC LD AMP
VC
VCC
+
–
5
VC
VC
VC
VCC
VEE
+
–
VC
+
–
VC
+
–
+
–
VC
+
–
RF EQ AMPRF SUMMING AMP
VC
ERROR AMP
FOCUS
14
13
VEE
VC
VC
VC BUFFER
TRACKING
ERROR AMP
HOLD
AGCVTH
LD
PD
A
B
C
D
VEE
F
E
VC
VCC
LC/PD
LD ON
HOLD SW
RF BOT
RFTC
RF 1
RF 0
RFE
FE
TE
AGCCONT
(50%/30%
OFF)
28 27 26
+ –
25 24 23 22 21 20 19 18
1 2 3 4 5 6 7
INTERFACE
MUTE
LEVEL SHIFT
INTERFACE
F
R
RF
RF
INTERFACE
R
F
R
F
17 1516
111098 12 1413
VCC
VREF
VCC
VCC
VCC
VCC
VREF NC SPIN SFDR SRDR CAPS GND MUTE VCC SL– SL+ SP– SP+
VREFOUT
FFDR
FRDR
CAP1
TFDR
TRDR
CAP2
GND
VREFIN
VCC
T+ T–
F– F+
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6-25. IC BLOCK DIAGRAMS
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