Sony SSC-DC593 - Page 45

5-5
SSC-DC593/DC593P/DC598P (E)
CXD3151R (SONY)
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50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
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31
30
29
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25
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23
22
21
20
19
18
17
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
CCD CAMERA SIGNAL PROCESSOR
—TOP VIEW—
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I
I
—
—
I
I
I
I
I
I
I
I
—
—
O
I
AD9
AD8
VCC
GND
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
VCC
MCK
MCKD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I
I
—
—
I
I
I
I
I
I
I
I
—
—
I
I
TIN9
TIN8
VCC
GND
TIN7
TIN6
TIN5
TIN4
TIN3
TIN2
TIN1
TIN0
GND
VCC
XRST
ZDET
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I
I
—
—
O
O
O
O
O
O
O
—
—
O
O
O
TGVD
TGHD
VCC
GND
WD9
WD8
WD7
WD6
WD5
WD4
WD3
GND
VCC
WD2
WD1
WD0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I
I
—
—
I
O
I
I
I
I
I
—
—
I
O
O
XCS
SCK
VCC
GND
SI
SO
TEST3
TEST2
TEST1
TEST0
LID
GND
VCC
EID
ATGHD
ATGVD
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
INPUTS
AD0 - AD9
EID
LID
MCKD
SCK
SI
TEST0 - TEST3
TGHD
TGVD
TIN0 - TIN9
XCS
XRST
ZDET
OUTPUTS
ATGHD
ATGVD
MCK
SO
WD0 - WD9
: A/D SIGNAL
: EXPOSURE TIME DISCRIMINATION
: LINE DISCRIMINATION
: MASTER CLOCK
: SERIAL CLOCK
: SERIAL DATA
: TEST
: HORIZONTAL SYNC
: VERTICAL SYNC
: TEST
: CHIP SELECT FOR SERIAL COMMUNICATION
: RESET
: DEFECT COMPENSATION PULSE
: PHASE ADVANCE HORIZONTAL SYNC SIGNAL OUTPUT FOR TG
: PHASE ADVANCE VERTICAL SYNC SIGNAL OUTPUT FOR TG
: DEMULTIPLY CLOCK
: SERIAL DATA
: WIDE DYNAMIC RANGE DATA
LONG/SHORT TIME
EXPOSURE PICTURE
SYNCHRONIZATION
59
LID
62
EID
32
ZDET
LONG
LONG
SHORT
YLONG
YSHORT
CLONG
SHORT
1, 2,
5 - 12
AD0 - AD9
CLAMP
FLICKER
COMPENSATION
LONG/SHORT
COMP.
C GAIN
ADJ.
LONG/SHORT
COMP.
Y GAIN
ADJ.
Y/C
SEP.
Y/C
SEP.
COMPLEMENTARY
COLORS BALANCE
COMPLEMENTARY
COLORS BALANCE
DATA
INTEGRATION/
COUNT
CSHORT
COMPRESSION
COMPRESSION
C
CMIX
YGAIN
CGAIN
YMIX
Y
Y/C COMP.
BLACK
ADD.
WD0 - WD9
37 - 43,
46 - 48
GAIN
LUT
GAIN SIG. GEN.
FLARE
COMPENSATION
SERIAL I/F
53
SI
50
SCK
49
XCS
SO
54
SYNC
GEN.
33
TGVD
31
XRST
34
TGHD
64
ATGVD
63
ATGHD
10
10
CLAMP
IC