Power supplies AN4488
8/44 DocID026304 Rev 3
2.1.3 Voltage regulator
The voltage regulator is always enabled after reset. It works in three different modes
depending on the application modes.
• in Run mode, the regulator supplies full power to the 1.2 V domain (core, memories
and digital peripherals)
• in Stop mode, the regulator supplies low power to the 1.2 V domain, preserving the
contents of the registers and SRAM
• in Standby mode, the regulator is powered down. The contents of the registers and
SRAM are lost except for those concerned with the Standby circuitry and the Backup
domain.
Note: Depending on the selected package, there are specific pins that should be connected either
to V
SS
or V
DD
to activate or deactivate the voltage regulator. Refer to section “Voltage
regulator “ in datasheet for details.
2.2 Power supply schemes
The circuit is powered by a stabilized power supply, V
DD
.
Caution: The V
DD
voltage range is 1.8 V to 3.6 V (down to 1.7 V with some restrictions, see relative
DataSheets for details)
• The V
DD
pins must be connected to V
DD
with external decoupling capacitors: one
single Tantalum or Ceramic capacitor (min. 4.7 µF typ.10 µF) for the package + one
100 nF Ceramic capacitor for each V
DD
pin.
• The V
BAT
pin can be connected to the external battery (1.65 V < V
BAT
< 3.6 V). If no
external battery is used, it is recommended to connect this pin to V
DD
with a 100 nF
external ceramic decoupling capacitor.
• The V
DDA
pin must be connected to two external decoupling capacitors (100 nF
Ceramic + 1 µF Tantalum or Ceramic).
• The V
REF+
pin can be connected to the V
DDA
external power supply. If a separate,
external reference voltage is applied on V
REF+
, a 100 nF and a 1 µF capacitors must
be connected on this pin. In all cases, V
REF+
must be kept between (V
DDA
-1.2 V) and
V
DDA
with minimum of 1.7 V.
• must be kept between 1.65 V and V
DDA
.
• Additional precautions can be taken to filter analog noise:
–V
DDA
can be connected to V
DD
through a ferrite bead.
–The V
REF+
pin can be connected to V
DDA
through a resistor (typ. 47 Ω).
• For the voltage regulator configuration, there is specific BYPASS_REG pin (not
available on all packages) that should be connected either to V
SS
or V
DD
to activate or
deactivate the voltage regulator specific.
– Refer to Section 2.3.6 and section "Voltage regulator" of the related device
datasheet for details.
• When the voltage regulator is enabled, V
CAP1
and V
CAP2
pins must be connected to
2*2.2 µF LowESR < 2Ω Ceramic capacitor (or 1*4.7 µF LowESR < 1Ω Ceramic
capacitor if only V
CAP1
pin is provided on some packages).
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