ST STM32L4 Series - Page 103

Contents
1 About this document ..............................................................2
1.1 Purpose and scope .............................................................2
1.2 Normative references ...........................................................2
1.3 Reference documents...........................................................3
2 Device development process ......................................................4
3 Reference safety architecture ......................................................5
3.1 Safety architecture introduction ...................................................5
3.2 Compliant item.................................................................5
3.2.1 Definition of Compliant item ................................................5
3.2.2 Safety functions performed by Compliant item ..................................5
3.2.3 Reference safety architectures - 1oo1.........................................6
3.2.4 Reference safety architectures - 1oo2.........................................7
3.3 Safety analysis assumptions .....................................................8
3.3.1 Safety requirement assumptions .............................................8
3.4 Electrical specifications and environment limits .....................................9
3.5 Systematic safety integrity .......................................................9
3.6 Hardware and software diagnostics ...............................................9
3.6.1 Arm
®
Cortex
®
-M4 CPU ...................................................10
3.6.2 System bus architecture/BusMatrix ..........................................16
3.6.3 Embedded SRAM .......................................................17
3.6.4 Embedded Flash memory .................................................21
3.6.5 Firewall (FW)...........................................................26
3.6.6 Power controller (PWR) ..................................................26
3.6.7 Reset and clock controller (RCC) ...........................................29
3.6.8 General-purpose input/output (GPIO) ........................................31
3.6.9 Debug system or peripheral control..........................................33
3.6.10 System configuration controller (SYSCFG) ....................................34
3.6.11 Direct memory access controller (DMA/ DMA2D/ DMAMUX))......................35
3.6.12 Chrom-Art Accelerator controller (DMA2D) ....................................38
3.6.13 Chrom-GRC™ (GFXMMU) ................................................39
UM2305
Contents
UM2305 - Rev 10
page 103/110