9
Synchronization with distributed clocks
ID 441896.05
WE KEEP THINGS MOVING
Operation manual
46
Information
This information is for the developers of the EtherCAT master software.
Please remember that there is a fundamental difference between ECS
5000 boards with hardware status HW 7 and HW 8: Boards up to HW
7 use the ESC20 as the EtherCAT slave controller while boards starting
with HW 8 use the ET1100.
To activate synchronization, the master must, among others, also write
the EtherCAT slave controller register with the System Time name
starting at address 0x0910.
With the ECS20, the register has 32 bits while, with the ET1100, the
register has 64 bits. If, with the ET1100, not all 64 bits are written
correctly, synchronization cannot start.
If you activate synchronization on the side of the EtherCAT master,
please note this change and read the "Hardware Data Sheet ET1100"
for more information. Pay particular attention to chapter "9.1 Clock
Synchronization" and the section there called "Definition of the System
Time" and also chapter "2.43.2 Time Loop Control Unit" with the
description of all the bits. Obtain advice on this subject from the
specialists of ETG.
If your software on the EtherCAT master must be able to decide which
EtherCAT slave controller is present, you can read this as a byte from
the Type of EtherCAT controller register at the address 0000
hex
. The
boards with the ESC20 return the value 02
hex
while boards with the
ET1100 return the value 11
hex
.
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