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X10SRL-F User’s Manual
Short Duration Power Limit
This item displays the time period during which short duration power is main-
tained. The default setting is 0.
Package Clamping Limit2
Use this item to set the limit on power performance states for the processor
operating in turbo mode, with P0 being the state with the highest frequency
(clock speed) and power (consumption), and P1, a step lower in performance
than P0, with its frequency and voltage scaled back a notch. The options are
Between P1/P0 and Below P1.
Chipset Conguration
North Bridge
This feature allows the user to congure the settings for the Intel North Bridge.
IIO Conguration
EV DFX (Device Function On-Hide) Feature
When this feature is set to Enable, the EV_DFX Lock Bits that are located on a
processor will always remain clear during electric tuning. The options are Dis-
able and Enable.
IIO1 Conguration
CPU SLOT3 PCI-E 3.0 X8
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT2 PCI-E 3.0 X4 (IN X8)
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT4 PCI-E 3.0 X8 (IN X16)
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT5 PCI-E 3.0 X8
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
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