Theory of Operation—2215A Service
B Delay Time Position Comparator
The B Delay Time Position Comparator circuit compares
the amplitude of the A Sweep sawtooth output voltage to
the dc voltage level set by B DELAY TIME POSITION
potentiometer R6440. The output of the comparator is used
to initiate a B Sweep and to control the B 2-Axis Logic
circuit switching.
The inputs to the comparator, U655, are the wiper volt
age of R9644 and the A Sweep voltage from the divider
network composed of R651, R652, and R653. Input voltage
ranges to the comparator are determined by VR645 and
R646 for the noninverting input and by R652 for the invert
ing input. Delay Start potentiometer R646 is adjusted in
conjunction with potentiometer R652 to set the B DELAY
TIME POSITION dial calibration.
The output of the comparator is enabled or disabled by
the strobe signal connected to pin 6. When the A Only signal
is HI, the comparator is enabled. When A Only is LO, the
output of the comparator is a high impedance and therefore
a HI is present on pin 9 of U680C.
B Sweep Logic
The B Sweep Logic circuitry utilizes signals from the as
sociated B Sweep circuitry to generate control signals for
both the B Miller Sweep and the B Z-Axis Switching Logic
circuits.
_ In the Runs After Delay mode, U660A places a LO on the
S input of U670A. During the previous hotdoff period,
U680D pin 13 strobed LO. The output of the flip-flop com
posed of U680C and U680D went Hl_and the output of
U660F went LO. With both the S and R inputs of U670A
LO, the Q output is HI to bias on Q709 and prevent the
B Miller Sweep from running. Once the A Sweep voltage at
U655 pin 3 exceeds the voltage at pin 2, the comparator
output will go LO. The flip flop composed of U680C and
U680D will change output states_and cause the R input of
U670A to be HI. The LO on the S input will then cause the
Q output of U670A to go LO. This will shut off Q709 and the
B Miller Sweep Generator will produce a linear ramp. If the
ramp voltage reaches about 12 V, sweep-end comparator
Q643 will turn on and cause the output of U665D to go HI.
The B Miller Sweep Generator will continue to run, but the
trace will be blanked because the B Gate line is HI which
reverse biases CR817. Once the ramp is at approximately
13 V, VR712 will conduct and prevent the voltage from in
creasing further.
The B Sweep Generator will be reset for another sweep
by one of two means. If the A Sweep doesn’t end before the
B Sweep, the Generator will not be reset until the Alt Sync
line goes from HI to_LO to change the U680C-U680D flip-flip
output states. The R input of U670A will then be LO, caus
ing the Q output to be HI and reset the Generator. Depend
ing on the settings of the A and B SEC/DIV switches, the A
Sweep may end before the B Sweep. If this occurs, the Alt
Sync line will go LO at the end of the A Sweep and cause an
immediate resetting of the Generator. In either case, a new
sweep will be initiated the next time the A Sweep voltage at
U655 pin 3 exceeds the voltage at pin 2.
When not in the Runs After Delay mode, the output of
U660A is HI and U670A has a HI on both the S and D
inputs. The circuitry connected to the R input of U670A
functions as described above. When the output of U660F
goes HI, U670A is no longer held reset and the first B trigger
signal from the collector of Q630 will clock through the HI on
the D input. The Q output of U670A will then go LO and a
B Sweep will be initiated.
Alternate Display Switching Logic
The Alternate Display Switching Logic circuitry controls
both the Horizontal Amplifier sweep switching and the B Z-
Axis Logic switching.
HORIZONTAL MODE switch S648 selects the input logic
levels that are applied to the circuitry. In the_A Horizontal
Mode, the S input of U670B is LO and the W input is HI.
This holds U670B set and allows only the A Sweep to be
passed to the Horizontal Amplifier. In the B Horizontal
mode, the set input of U670B is HI and the reset input is LO
to hold U670B reset and allow only the B Sweep to reach
the Horizontal Amplifier.
With S648 set to ALT, and for all settings of the VERTI
CAL MODE switches except BOTH-ALT, the Valt signal ap
plied to U660E and the S and R inputs of U670B are all HI.
The LO output of U660E causes the output of U680B to be
HI, and whenever the Alt Sync signal applied to pin 1 goes
LO, the gate output will change from LO to HI and clock
U670B. The outputs of U670B will therefore toggle with
each Alt Sync signal transition to alternately enable the A
and B Sweeps to reach the Horizontal Amplifier. Whenever
the B Sweep is selected for the Horizontal Amplifier, the Q
output of U670B will be HI. This HI is applied to U665C pin
9, and since pin 10 is also HI, the Sep signal from U665C
will be LO to enable the A/B Sweep Separation circuitry.
When the CH 1-BOTH-CH 2 VERTICAL MODE switch is
set to BOTH, the ADD-ALT-CHOP switch becomes func
tional. In the ALT VERTICAL MODE position, the Valt signal
is LO, the Halt signal is HI, and the CH 1 Selected signal is a
TTL square wave that switches states at the end of the A
Sweep. Input pin 4 of U680B will be HI and the gate output
will be the inverse of the CH 1 Selected signal. This output
3-12
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