When data has been read into the controller from the
GPIB bus, the GPIBINT (GPIB interrupt) request is
asserted, telling the System IlP that GPIB data is avail-
able. To receivethe data, the System IlP reads the GPIB
Controller internal data register, automaticallyresetting the
interrupt request.
The GPIB Controller is nowinitialized and begins
watching the handshakelines on the GPIB bus, looking for
a data transfer to be initiated by another GPIB device on
the bus. Data transfer may also be initiated by the System
IlP by writing data into the GPIB Controller data register.
In either case, activity on the GPIB bus follows the
sequencespresentedin Figures3-11 and 3-12.
When power is first applied, the GPIBRESET signal
from register U754 holds GPIB Controller U630 in its reset
state. The System IlP then removes the reset and begins
to initializethe internal registers of the GPIB Controller.To
write data into the registers,the System IlP writes data to
the memory-mapped addresses between 6800h and
6807h. These addresses produce a LO GPIBSEL and a
LO address bit A3 applied to U332B and enablethe GPIB
Controller. Data is written to the internal register defined
by addressbits AO-A2.
GPIB data transfers are done under control of U630, a
GPIB Controller integrated circuit. The controller automati-
cally producesproper handshakingand data direction con-
trol. Data is transferred to and from the GPIB bus through
bidirectional buffer U624. Handshaking signals are
transferred to and from the GPIB bus via the handshaking
bidirectional buffer, U720. Data transfers between the
GPIB Controller and the System IlP are through bidirec-
tional buffer U532.
The GPIB interface provides the 2430 with an electrical
interface adherent to the IEEE 488-1980 Standard using
protocols defined in the Tektronix GPIB Codes and For-
mats Standard.
GPIB
The System I/O circuits (diagram20) provide methods
of getting various types of signals or voltages into and out
of the 2430. These include a GPIB interface, an XY
Recorder interface, Word-Trigger interface, an audio bell,
and the probe-power connectors used to supply power to
active probes.
SYSTEM I/O
3-78
Other adjustable level-settingcircuits include"Orthog-
onality" Alignment pot A305, used to rotate the beam
alignmentafter vertical deflection.This adjustmentcontrols
the amount of current through the Y-Axis alignment coil
around the neck of the crt and is set to produce precise
perpendicular alignment between the X- and Y-Axis
deflections. The TRACE ROTATION adjustment pot,
A1077, is a front-panel control. The effect of the adjust-
ment is similar to the Y-Axis Alignment pot, but when
adjusted, it rotates both the X-Axis and the Y-Axis
deflectionson the face of the crt. A final adjustable level-
setting control is the Geometry pot R200, adjusted to
optimizedisplaygeometry.
The operational amplifier and transistor of the Edge-
Focus circuit are arranged as a feedback amplifier with
R279 and R179 setting the stage gain. Gain of the
amplifier is equal to the attenuation factor of divider net-
work R278 and R277; so, total overall gain of the stage
from the wiper of R300 to the collectorof 0269 is equal to
unity. The offset voltage between lens elements is set by
the ratio of R279 and R179 and the
+
10 V reference
applied to R179. This arrangement causes the two volt-
ages applied to the third quadrapole lens to track each
other over the entire range of Edge Focus
adjustment R300.
Other CRT Control Circuits
The CRT Control Circuits produce the voltages and
current levelsnecessaryfor the crt to operate.Operational
amplifier U168B, transistor 0269, and associated com-
ponents form an Edge-Focuscircuit that establishes the
voltages for the elementsof the third quadrapolelens. The
positive lens element is set to its operating potential by
Edge Focus adjustment pot R300 (via R393).This voltage
is also divided by R278 and R277 and applied to the
noninvertinginput of U168B to control the voltage on the
other elementof the third lens.
Neon lamps DS490 and DS491 prevent arcing inside
the crt by preventing the control grid and cathode from
becomingtoo widely separatedin voltage.
The fast-rise and fast-fall transitions of the Z-Axis sig-
nal are coupledto the crt control grid through capacitor D.
This ac-coupled fast-path signal sends the crt electron
beam to the new intensity level, then the slower DC
Restorer path "catches up" to handle the dc and low-
frequencycomponentsof the Z-Axis drive signal.
Theory of Operation-2430 Service
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