3-87
To detect whether a signal is interlaced (two vertical-
sync pulses per frame) or non-interlaced (only one
vertical-sync pulse per frame), flip-flop U310B is clocked to
transfer the level of the HCLK signal on the D input to
the
0
output by the VERTSYNC clock at the start of a
vertical-sync period. For non-interlaced displays, the
FIELD-SYNC GENERATOR. The Field-Sync Generator
produces the FIELD signal used in identifying the individual
fields of picture information. For interlaced-scan signals,
the signal identifies which field a given line of picture infor-
mation belongs to (exceptions are explained in the Line
Counter description); while, for non-interlaced-scan sig-
nals, it toggles to indicate vertical sync. The circuit con-
sists of an Interlace/non-Interlace Detector, a Vertical-Sync
Latch (interlaced), and a Vertical-Sync flip-flop
(non-interlaced).
VERTICAL SYNC. The Vertical Sync circuitry outputs
pulses for both the Field 1 and the Field 2 vertical-sync
times. These VERTSYNC pulses are used to toggle the
Field Sync Generator. The VERTSYNC signal is produced
by clocking the level of the COMPSYNC signal on the D
input (pin 5) of U310A into that flip-flop using the inverted
two-times horizontal clock 2XH. Figure 3-14 shows that
only during a vertical-sync interval will the COMPSYNC
signal be HI on the rising edge of the
2XH
clock. At all
other (non-vertical sync) times, the COMPSYNC signal will
be LO on the rising edge of the 2XH clock. Thus, the
0
output of flip-flop U310A will be clocked HI during vertical-
sync intervals for VERTSYNC, and it will be clocked LO
during the rest of the field.
DELAYED HORIZONTAL CLOCK. The Delayed Hor-
izontal Clock (DLY'D HCLK) is used to remove alternate
equalizing pulses and serration pulses from the
composite-sync waveform in order to maintain precise
sync for horizontal line counting. The PLL-generated HCLK
signal from the
0
output of U220B is clocked into U220A
by the 2XH pulse from NOR-gate U308A (acting as an
inverter). The inversion of the two-times clock delays the
0
output of flip-flop U220A by one-quarter of a horizontal
clock (HCLK) cycle. The quarter-cycle delay enables the HI
portion of the output (applied to U420B via R210) to mask
the alternate, unwanted equalization and serration pulses
(occurring at twice the horizontal-sync rate) from the HOR-
IZCLK output by preventing U420B, in the Pulse Stretcher
circuit, from switching during those time periods. The
same signal masks the unwanted equalization pulses from
the PLL inputs by disabling NOR-gates U308B and U308C
from passing signals to compare during the DLY'D HCLK
HI state. All the vertical-sync serration pulses are elim-
inated from the PLL Phase Comparator input by the HI
state of the VERTSYNC signal applied to the input
NOR-gates.
Theory of Operation-2430 Service
The DLY'D HCLK is shifted one-quarter HCLK cycle.
When the DLY'D HCLK is HI, the outputs of both NOR-
gates at the inputs to the PLL Phase Comparator are held
LO, and the alternate equalizing pulses of composite-sync
signal are prevented from passing to the PLL Phase Com-
parator. The vertical-sync serrations are prevented from
passing through NOR-gate U308B by the HI VERTSYNC
signal applied during vertical-sync times. Both types of
unwanted pulses are thereby eliminated from the Phase
Comparator inputs. The remaining sync pulses to be com-
pared with the HORIZCLK signal are then only at the
horizontal-sync frequency, and the VCO output frequency
shifts slightly as necessary to bring that frequency to pre-
Ciselytwice the horizontal-sync rate (2XH). The charge on
capacitor C322 holds the VCO to that output frequency
throughout the vertical-sync period when all serration
pulses are disabled from the Phase Comparator input and
no comparisons are being made.
When lock is achieved, the phase difference between
the two input signals becomes very small. The PLL LOCK
pulse output level remains in the HI state (no error) long
enough that C330 is allowed to charge positive and turn
off transistor
0330.
UNLOCK then goes LO to remove the
resets from flip-flops U310A and U220A, allowing them
operate, and TVCLAMP goes LO to enable the Channel 2
Vertical Display Clamp circuit. Unwanted equalizing pulses
and the vertical-sync serrations are now prevented from
passing to PLL Phase Comparator inputs by the DLY'D
HCLK (delayed horizontal clock) and VERTSYNC signals
applied to the PLL Phase Comparator Input NOR-gates,
U308B and U308C (see Figure 3-13).
A similar signal (PLL LOCK) from pin 1 of the Phase
Comparator is integrated by R326 and C330. If the PLL is
not locked onto the input signal, the PLL LOCK output
remains in the LO state long enough to be sensed by the
PLL Unlock Detector. The long LO state of the PLL LOCK
signal discharges C330 negative enough with respect to
the emitter voltage of
0330,
that the transistor becomes
biased on. The collector voltage of
0330
will then go high,
and Vertical Sync flip-flop U310A and Delayed Horizontal
Clock flip-flop U220A will both be reset by the HI
UNLOCKED signal. With U220A and U310A both reset,
the DLY'D HCLK and VERTSYNC signals are held LO,
and the equalizing pulses and vertical-sync serrations are
no longer prevented from passing through NOR-gate
U308B. The PLL Phase Comparator then sees the entire
input signal during attempts to lock on so that locking will
occur in the proper range. While the unlocked condition
exists, the Channel 2 Vertical Display Clamp circuit is held
disabled (via R328) by the HI state of TVCLAMP to
prevent an invalid offset from being sent to the Channel 2
Vertical Preamplifier.
slight lag prevents the possibility of jitter in the HORIZCLK
signal going to clock TV Trigger flip-flop U524B.
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