RELATIVE FIELD ADJUSTMENTS. For non-System M
television signals (line one coincident with the FIELD sync
pulse), the line-adjustment requirements described above
require that the first three lines of either field be counted
relative to the previous FIELD pulse.
3. The counter outputs merely arm the trigger circuit,
with the next line sync producing the actual trigger; there-
fore, line count must be reduced again by one.
2. The counters cannot produce a "zero-count" delay;
i.e., the counter output goes LO one count (line) after the
counter reaches zero. Even when set to zero, a count
must still occur; so the line count must be reduced by one
again.
1. The HORIZCLK coincident with a switch in the
FIELD indicator does not produce a count. Since the
FIELD change doesn't enable the opposite counter in time
to catch the rising edge of the HORIZCLK (responsible for
the change), the preloaded line count must be reduced
by one.
LINE COUNT ADJUSTMENTS. Depending on the type
of signal being triggered upon (System M or non-System
M) and the desired line for trigger, the System JlP adjusts
both the numbers preloaded to the coynters and the field
to which the assigned line-count relates. These line-count
and relative-field adjustments are required for the following
reasons.
Once the proper setup data (defining counter mode and
line number) is written to the Line Counter, the enabled
counter will begin counting horizontal clock pulses (lines).
Counters are alternately started as the FIELD signal tog-
gles, and counters 1 and 2 produce a LO output when
their predefined counts are reached. Counter 3 is used to
determine the number of LINES in a FIELD (of FIELD 2 if
in an interlaced system). The System JlP checks the "pre-
vious field" line count by reading the counter contents via
the data bus.
To differentiate it from the GPIB circuitry (which also
answers for the same block of decoded addresses), the
Video Option uses address bit A3 as a second chip select.
Specific registers within the Line Counter are addressed
using address lines AO-A2 applied to the register-select
inputs. Reading and writing of the selected register is con-
trolled by the System JlP using the WR select line while
the E (enable) clock synchronizes transfers to the System
JlPrate.
3-88
The Line Counter is enabled whenever its address
block is decoded by the system Address Decode circuitry.
LINE COUNTERS. Line Counter U530 contains three
programmable counters (at decoded addresses 6808h
through 680Fh) that are set by the System Processor to
determine when the chosen line number in the field
selected for triggering is reached. The various control
registers of the counter are set up to count horizontal
clock pulses (lines) to determine line location in the field.
For interlaced displays, the output from U310B will tog-
gle. This will alternately turn transistor U420A on and off
at the vertical-field rate. The first time U420A gets turned
on by an interlaced-system signal, it discharges C426 and
turns
0422
on. Capacitor C426 will charge positive
through R429 and R428 when U420A turns off, but the
long time constant of the charging path prevents the
charge from getting positive enough to reassert the reset
to U430B before the next toggle cycle once again
discharges the capacitor. Flip-flop U430A is held set by
the HI TVINTERLACED (interlaced) signal asserted from
the collector of
0422,
and CR336 is reverse biased to iso-
late U430A from the FIELD signal line. The resulting FIELD
signal, as a result of the output of flip-flop U430B, will be
HI for all lines in Field 1 and LO for all lines in Field 2 (with
a few exceptions that are explained in the Line Counters
description).
The
0
from pin 12 of U310B controls two other flip-
flops U430A and U430B, through the circuit action of
transistors U420A and
0422.
If the output of U310B is not
toggling (non-interlaced signals), transistor U420A will be
turned off by pull-down resistor R426. This allows the base
bias voltage of
0422
to go positive as C426 charges
through R429 and R428. Soon,
0422
is biased off and
flip-flop U430B becomes reset. The reset on U430B from
C426 holds the
0
output HI to reverse bias CR334 and
isolate the
0
output from the FIELD signal line. At the
same time, the LO TVINTERLACED signal applied to the
set input of U430A from the collector of
0422
enables that
flip-flop to toggle on the rising edges of the vertical-sync
pulses applied to the clock input (pin 3). This toggling is
required to reinitialize the counters after they have counted
their last lines. The TVINTERLACED signal is also applied
to the Processor Miscellaneous Buffer (U854, diagram 1)
where it may be read by the System JlP to determine
whether the video signal is interlaced or non-interlaced.
The System JlP must be able to determine this information
to properly control the line counting.
vertical-sync rising edge always occurs during a HI portion
of the HCLK signal, and the
Q
output of U310B will be
clocked HI; while, for interlaced displays, the
Q
output will
alternate between HI and LO.
Theory of Operation-2430 Service
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