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When display clamping of the Channel 2 signal is not
enabled, BCLAMPENA will be set LO, turning U420D on.
The HI on the collector of U420D turns on U410B, U410C,
and 0420 and turns off 0710 via U710A. Any enabling
currents to offset amplifiers U514 or U520 are shunted
through U410B and U410C respectively. With FET 0420
on, the input to U710D will be grounded. This disables the
CLAMP SWITCHING. The Clamp Switching circuit
enables and disables the effect of the Channel 2 Vertical
Display Clamp. The clamp circuit operation may be
switched to provide correct clamping for either inverted or
noninverted video signals.
Offset gain of Channel 2 Preamplifier U320 is set higher
when the CH2 VOLTS/DIV switch is set to 2 mV, 5 mV,
10 mV, 100 mV, or 1 V/Div. At those VOLTS/DIV settings,
the FASTCLAMP bit is set LO to turn on U420E. This
turns FET 0419 on and places C520 in parallel with C522
thus increasing the size of the hold capacitance. This
slows down the loop response at the "more sensitive"
offset gain setting of the Channel 2 Preamplifier to prevent
oscillation.
The Channel 2 Pickoff (CH2 PO) signal from the Chan-
nel 2 Preamplifier is applied through a low-pass filter
formed by R524 and C514. The filter removes all the high-
frequency components from the composite video signal,
but its purpose is to specifically remove the color-burst
modulation from the back-porch of the sync pulses. The
filtered sync pulse is then amplified with respect to ground
during its back-porch interval either by operational
amplifier U514 or by operational amplifier U520, depending
on the display polarity chosen by the operator. The
selected comparator, when gated on (via U410A and either
R410 or R411) during the back-porch interval, produces a
de-onset voltage used to shift the back-porch level of the
displayed channel 2 signal to zero volts. Capacitor C522
acts as a hold capacitor to maintain a constant dc offset
to the Channel 2 Vertical Preamplifier between back-porch
samples. Operational amplifier U710D buffers the offset
signal to the Channel 2 Preamplifier.
CH2 VERTICAL DISPLAY CLAMP. The Channel 2
Display Clamp circuit clamps the back-porch level of the
triggered-display signal near the on-screen zero-volt refer-
ence. This allows automatic positioning of the display on
the crt when probing various points with differing dc levels
and removes vertical jitter that would be caused by 60-Hz
hum riding on the television signal.
each holdoff interval. The resulting display will be stable
with respect to horizontal sync pulses but will not be
stable with respect to the vertical sync pulses.
Theory of Operation-2430 Service
When TV Line Coupling mode is selected, the LlNECPL
bit from the Video Option Control Register will be set HI.
This causes flip-flop U524A to be immediately armed when
A trigger holdoff ends by forcing a set signal to pin 4 of
that flip-flop through NAND-gate U541B. In this mode, a
trigger will occur on the first line sync following the end of
Assuming TV Line Coupling mode is not active, the
LlNECPL (line coupling) bit applied to U541 B pin 5 will
be
LO, and arming flip-flop U524A will be enabled. When the
Line Counter has counted the proper number of lines rela-
tive to the Processor-selected field, flip-flop U524A will
be
clocked. This produces a HI "armed" level applied to the
reset input of trigger flip-flop U524A that releases the
reset condition of the flip-flop. The next HORIZCLK pulse
(line)then clocks a LO to the 0 output, TVTG, that defines
the trigger point in the acquisition record. The TVTG out-
put is reset HI when trigger holdoff (ATHO) goes HI to
reset the flip-flop via U424C and U524A.
In the Video Option, as in the main Trigger Generator a
trigger signal is inhibited from being produced during
trigger holdoff. For the holdoff period, the ATHO (A-trigger
holdoff) signal applied to U424C is HI to hold arming flip-
flop U524A reset which, in turn, holds trigger flip-flop
U524A reset. When the holdoff processing cycle is com-
pleted, the ATHO signal goes LO to remove the reset from
U524A and enable triggering.
TV TRIGGER GENERATOR. The TV Trigger Generator
circuit produces the signal to trigger the Oscilloscope at
the designated horizontal line. The output from the Line
Counter arms the TV Trigger Generator circuit, enabling a
trigger to be produced on the next line-sync pulse. Gen-
eration of a TV trigger from the circuit is enabled by a HI
TVENA (TV-enable) bit from Video Option Control Register
U750 (diagram 20).
As stated in the "Line Count Adjustments," the trigger
arming pulse occurs one line count prior to reaching the
selected trigger line. Depending on whether the System
Processor has selected the arming pulse relative to Field 1
or Field 2, either NAND-gate U541 C or NAND-gate U541D
will be enabled by a control bit (FLD1 or FLD2) from Video
Option Control Register U750. The selected pulse, when it
occurs, is passed through the enabled gate, through
U541 A and U424D, and appears as a clock pulse at the
trigger-arm flip-flop, U524A.
Since, by definition, System-M fields begin numbering
lines three lines before the vertical field-sync occurs, and
due to the line-adjustment requirements described above,
the first six lines of System-M fields must be counted rela-
tive to the previous FIELD pulse.
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