6-49
3. While the test is running, test U654 pin 17 for steady-state HI value. If HI and DCOK fails, then
replace U654. If LO, then check the power supply voltages and the DCOK AND circuit. If supply
voltages are not correct, troubleshoot the low-voltage power supply and regulators; if voltages are
correct, troubleshoot A16U395 and associated components (schematic diagram 23).
2. Run test 2120 in CONTINUOUS MODE and check for INTREG chip select on pins 1 and 19 of
Interrupt Register U654. If not present, troubleshoot the System Address Decoding circuitry
(U884, U862, U866A, U870B, and associated components) for proper inputs and outputs.
Now using CH2 probe:
1. Set up the test scope as per Step 1 of the 2110 troubleshooting procedure.
If test
=
FAIL then look for failure using the following steps:
Troubleshooting Procedure:
The power supply sends a TTL signal to the interrupt register to inform the System J.LPof the logic
AND of the power supply voltages. DCOK tests INTREG (bit 7). If
=
1, the test result
=
PASS; other-
wise, the result
=
FAIL.
Testing Method:
Interrupt Register A12U654 (schematic diagram 1) and DCOK logic circuitry A16U395 and associated
components (schematic diagram 23):
2120
DCOK U654
5. While selected, check that U854 pin 11 is set to the state of U860 pin 19. If DIAGOfailed and the
chip selects to U854 and the signal to U854 pin 11 are ok, then U854 is probably defective.
4. Test for a chip select at U854 pins 1 and 19 (LO enables). If not correct, troubleshoot System
Address Decode circuitry (U884, U862, and U866).
3. Check that U860 pin 19 clocks from LO-to-HI and remains HI after the trigger strobe pulse returns
to LO. If not, replace U860.
2. Run test 2110 in CONTINUOUS mode and check for clock activity at U860 pin 11 (clocks on LO-
to-HI transition close to the end of the trigger strobe pulse); if not, troubleshoot its clocking cir-
cuitry (U884, U862, and U866).
Now using CH2 probe:
1. On the test scope, connect CH 1 to J125 pin 15. Select Slope, + (plus); Trigger Source, CH 1;
Trigger Level, 1 V; CH 1 and CH 2 input coupling, DC; CH 1 and CH 2 VOLTS/DIV, 2 V. This
step provides a positive, TTL-level trigger strobe (or pulse) for validation of the signal being tested
while a test is running. The test scope setup will be used in each of the Registers troubleshooting
procedures.
If test
=
FAIL then look for failure using the following steps:
Sets PCREG (bit 07)
=
0 and tests for
=
0 (stuck at one). Sets PCREG (bit D7)
=
1 and tests for
=
1 (stuck at zero). If both tests pass, the result flag is set to PASS; otherwise, it is set to FAIL.
Testing Method:
Page Control Register (PCREG) A12U860 (schematic diagram 1):2110
DIAGO
Table
6-6
(cont)
Maintenance-2430 Service
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